DS39609A - page ii

2003 Microchip Technology Inc.

Information contained in this publication regarding device
applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications. No
representation or warranty is given and no liability is assumed by
Microchip Technology Incorporated with respect to the accuracy
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Use of Microchip's products as critical components in life
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Trademarks

The Microchip name and logo, the Microchip logo, K

MPLAB, PIC, PICmicro, PICSTART, PRO MATE and
PowerSmart are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.

FilterLab, microID, MXDEV, MXLAB, PICMASTER, SEEVAL
and The Embedded Control Solutions Company are registered
trademarks of Microchip Technology Incorporated in the U.S.A.

Accuron, dsPIC, dsPICDEM.net, ECONOMONITOR,
FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming,
ICSP, ICEPIC, microPort, Migratable Memory, MPASM, MPLIB,
MPLINK, MPSIM, PICC, PICkit, PICDEM, PICDEM.net,
PowerCal, PowerInfo, PowerTool, rfPIC, Select Mode,
SmartSensor, SmartShunt, SmartTel and Total Endurance are
trademarks of Microchip Technology Incorporated in the U.S.A.
and other countries.

Serialized Quick Turn Programming (SQTP) is a service mark of
Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their
respective companies.

� 2003, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.

Printed on recycled paper.

Microchip received QS-9000 quality system

certification for its worldwide headquarters,

design and wafer fabrication facilities in

Chandler and Tempe, Arizona in July 1999

and Mountain View, California in March 2002.

The Company's quality system processes and

procedures are QS-9000 compliant for its

PICmicro

�

8-bit MCUs, K

�

code hopping

devices, Serial EEPROMs, microperipherals,

non-volatile memory and analog products. In

addition, Microchip's quality system for the

design and manufacture of development

systems is ISO 9001 certified.

Note the following details of the code protection feature on Microchip devices:
�

Microchip products meet the specification contained in their particular Microchip Data Sheet.

�

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

�

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

�

Microchip is willing to work with the customer who is concerned about the integrity of their code.

�

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as "unbreakable."

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

2003 Microchip Technology Inc.

Advance Information

DS39609A-page 1

PIC18FXX20

High Performance RISC CPU:

� C compiler optimized architecture/instruction set:

- Source code compatible with the PIC16 and

PIC17 instruction sets

� Linear program memory addressing to 128 Kbytes
� Linear data memory addressing to 3840 bytes
� 1 Kbyte of data EEPROM
� Up to 10 MIPs operation:

- DC - 40 MHz osc./clock input
- 4 MHz - 10 MHz osc./clock input with PLL active

� 16-bit wide instructions, 8-bit wide data path
� Priority levels for interrupts
� 31-level, software accessible hardware stack
� 8 x 8 Single Cycle Hardware Multiplier

External Memory Interface
(PIC18F8X20 Devices Only):

� Address capability of up to 2 Mbytes
� 16-bit interface

Peripheral Features:

� High current sink/source 25 mA/25 mA
� Four external interrupt pins
� Timer0 module: 8-bit/16-bit timer/counter
� Timer1 module: 16-bit timer/counter
� Timer2 module: 8-bit timer/counter
� Timer3 module: 16-bit timer/counter
� Timer4 module: 8-bit timer/counter
� Secondary oscillator clock option - Timer1/Timer3
� Five Capture/Compare/PWM (CCP) modules:

- Capture is 16-bit, max. resolution 6.25 ns (T

/16)

- Compare is 16-bit, max. resolution 100 ns (T

)

- PWM output: PWM resolution is 1- to 10-bit

� Master Synchronous Serial Port (MSSP) module

with two modes of operation:
- 3-wire SPITM (supports all 4 SPI modes)

- I

CTM Master and Slave mode

� Two Addressable USART modules:

- Supports RS-485 and RS-232

� Parallel Slave Port (PSP) module

Analog Features:

� 10-bit, up to 16-channel Analog-to-Digital

Converter (A/D):
- Conversion available during SLEEP

� Programmable 16-level Low Voltage Detection

(LVD) module:
- Supports interrupt on Low Voltage Detection

� Programmable Brown-out Reset (PBOR)
� Dual analog comparators:

- Programmable input/output configuration

Special Microcontroller Features:

� 100,000 erase/write cycle Enhanced FLASH

program memory typical

� 1,000,000 erase/write cycle Data EEPROM

memory typical

� 1 second programming time
� FLASH/Data EEPROM Retention: > 40 years
� Self-reprogrammable under software control
� Power-on Reset (POR), Power-up Timer (PWRT)

and Oscillator Start-up Timer (OST)

� Watchdog Timer (WDT) with its own On-Chip

RC Oscillator for reliable operation

� Programmable code protection
� Power Saving SLEEP mode
� Selectable oscillator options including:

- 4X Phase Lock Loop (of primary oscillator)
- Secondary Oscillator (32 kHz) clock input

� In-Circuit Serial ProgrammingTM (ICSPTM) via

two pins

� MPLAB

�

In-Circuit Debug (ICD) via two pins

CMOS Technology:

� Low power, high speed FLASH technology
� Fully static design
� Wide operating voltage range (2.0V to 5.5V)
� Industrial and Extended temperature ranges

Device

Program Memory

Data Memory

I/O

10-bit A/D

(ch)

CCP

(PWM)

MSSP

USART

Timers

8-bit/16-bit

Ext

Bus

Bytes

# Single Word

Instructions

SRAM

(bytes)

EEPROM

(bytes)

SPI

Master

PIC18F6520

32K

16384

2048

1024

2/3

PIC18F6620

64K

32768

3840

1024

2/3

PIC18F6720 128K

65536

3840

1024

2/3

PIC18F8520

32K

16384

2048

1024

2/3

PIC18F8620

64K

32768

3840

1024

2/3

PIC18F8720 128K

65536

3840

1024

2/3

64/80-Pin High Performance, 1 Mbit Enhanced FLASH

Microcontrollers with A/D

2003 Microchip Technology Inc.

Advance Information

DS39609A-page 3

PIC18FXX20

Pin Diagrams (Cont.'d)

PIC18F8620

3
4
5
6
7
8
9
10
11
12
13
14
15
16

48
47
46
45
44
43
42
41

64 63 62 61

21 22 23 24 25 26 27 28 29 30 31 32

2/CS

*
*
*

3/A

4/A

5/A

6/A

RE7/

CCP

15**

RD0/P

0***

RD1/P

1***

RD2/P

2***

RD3/P

3***

RD4/P

4***

RD5/P

5***

RD6/P

6***

RD7/P

7***

***RE1/WR/AD9

***RE0/RD/AD8

RG0/CCP3

RG1/TX2/CK2

RG2/RX2/DT2

RG3/CCP4

MCLR/V

RG4/CCP5

RF7/SS

RF6/AN11

RF5/AN10/CV

REF

RF4/AN9
RF3/AN8

RF2/AN7/C1OUT

RB0/INT0
RB1/INT1
RB2/INT2
RB3/INT3/CCP2*
RB4/KBI0
RB5/KBI1/PGM
RB6/KBI2/PGC

OSC2/CLKO/RA6
OSC1/CLKI
V

RB7/KBI3/PGD

RC4/SDI/SDA
RC3/SCK/SCL
RC2/CCP1

0/A

AN6/

C2O

AN3/

4/T

RC1/T

I
/CCP

RC7

/RX

/DT1

RC5/SDO

0/A

/OE

RH1/

RH0/A

1
2

RH2/A18
RH3/A19

17
18

RH7/AN15
RH6/AN14

RH5/A

N13

RH4/A

N12

5/CE

J
4/

BA0

RJ7/UB
RJ6/LB

50
49

RJ2/WRL
RJ3/WRH

19
20

33 34 35 36

58
57
56
55
54
53
52
51

60
59

68 67 66 65

72 71 70 69

74 73

78 77 76 75

80-pin TQFP

PIC18F8720

* CCP2 is multiplexed with RC1 when CCP2MX is set.

** CCP2 is multiplexed by default with RE7 when the device is configured in Microcontroller mode.

*** PSP is available only in Microcontroller mode.

RC0/

/
T

13CLK

PIC18F8520

PIC18FXX20

DS39609A-page 4

Advance Information

2003 Microchip Technology Inc.

Table of Contents

1.0

Device Overview .......................................................................................................................................................................... 7

2.0

Oscillator Configurations ............................................................................................................................................................ 21

3.0

Reset .......................................................................................................................................................................................... 29

4.0

Memory Organization ................................................................................................................................................................. 39

5.0

FLASH Program Memory ........................................................................................................................................................... 61

6.0

External Memory Interface ......................................................................................................................................................... 71

7.0

Data EEPROM Memory ............................................................................................................................................................. 79

8.0

8 X 8 Hardware Multiplier ........................................................................................................................................................... 85

9.0

Interrupts .................................................................................................................................................................................... 87

10.0 I/O Ports ................................................................................................................................................................................... 103
11.0 Timer0 Module ......................................................................................................................................................................... 131
12.0 Timer1 Module ......................................................................................................................................................................... 135
13.0 Timer2 Module ......................................................................................................................................................................... 141
14.0 Timer3 Module ......................................................................................................................................................................... 143
15.0 Timer4 Module ......................................................................................................................................................................... 147
16.0 Capture/Compare/PWM (CCP) Modules ................................................................................................................................. 149
17.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 157
18.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (USART).............................................................. 197
19.0 10-bit Analog-to-Digital Converter (A/D) Module ...................................................................................................................... 213
20.0 Comparator Module.................................................................................................................................................................. 223
21.0 Comparator Voltage Reference Module................................................................................................................................... 229
22.0 Low Voltage Detect .................................................................................................................................................................. 233
23.0 Special Features of the CPU.................................................................................................................................................... 239
24.0 Instruction Set Summary .......................................................................................................................................................... 259
25.0 Development Support............................................................................................................................................................... 301
26.0 Electrical Characteristics .......................................................................................................................................................... 307
27.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 341
28.0 Packaging Information.............................................................................................................................................................. 343
Appendix A: Revision History............................................................................................................................................................. 347
Appendix B: Device Differences......................................................................................................................................................... 347
Appendix C: Conversion Considerations ........................................................................................................................................... 348
Appendix D: Migration from Mid-Range to Enhanced Devices .......................................................................................................... 348
Appendix E: Migration from High-End to Enhanced Devices............................................................................................................. 349
Index .................................................................................................................................................................................................. 351
On-Line Support................................................................................................................................................................................. 361
Systems Information and Upgrade Hot Line ...................................................................................................................................... 361
Reader Response .............................................................................................................................................................................. 362
PIC18FXX20 Product Identification System....................................................................................................................................... 363

2003 Microchip Technology Inc.

Advance Information

DS39609A-page 5

PIC18FXX20

TO OUR VALUED CUSTOMERS

It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at docerrors@mail.microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150.
We welcome your feedback.

Most Current Data Sheet

To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:

http://www.microchip.com

You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
� Microchip's Worldwide Web site; http://www.microchip.com
� Your local Microchip sales office (see last page)
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When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include liter-
ature number) you are using.

Customer Notification System

2003 Microchip Technology Inc.

Advance Information

DS39609A-page 7

PIC18FXX20

1.0

DEVICE OVERVIEW

This document contains device specific information for
the following devices:

This family offers the advantages of all PIC18 micro-
controllers - namely, high computational performance
at an economical price - with the addition of
high-endurance Enhanced FLASH program memory.
The PIC18FXX20 family also provides an enhanced
range of program memory options and versatile analog
features that make it ideal for complex, high
performance applications.

1.1

Key Features

1.1.1

EXPANDED MEMORY

The PIC18FXX20 family introduces the widest range of
on-chip, Enhanced FLASH program memory available
on PICmicro

�

microcontrollers - up to 128 Kbyte (or

65,536 words), the largest ever offered by Microchip.
For users with more modest code requirements, the
family also includes members with 32 Kbyte or
64 KByte.
Other memory features are:
� Data RAM and Data EEPROM: The PIC18FXX20

family also provides plenty of room for application
data. Depending on the device, either 2048 or
3840 bytes of data RAM are available. All devices
have 1024 bytes of data EEPROM for long-term
retention of non-volatile data.

� Memory Endurance: The Enhanced FLASH cells

for both program memory and data EEPROM are
rated to last for many thousands of erase/write
cycles - up to 100,000 for program memory, and
1,000,000 for EEPROM. Data retention without
refresh is conservatively estimated to be greater
than 40 years.

1.1.2

EXTERNAL MEMORY INTERFACE

In the unlikely event that 128 Kbyte of program memory
is inadequate for an application, the PIC18F8X20
members of the family also implement an External
Memory Interface. This allows the controller's internal
program counter to address a memory space of up to
2 MByte, permitting a level of data access that few 8-bit
devices can claim.

With the addition of new Operating modes, the External
Memory Interface offers many new options, including:
� Operating the microcontroller entirely from external

memory

� Using combinations of on-chip and external

memory, up to the 2 Mbyte limit

� Using external FLASH memory for reprogrammable

application code, or large data tables

� Using external RAM devices for storing large

amounts of variable data

1.1.3

EASY MIGRATION

Regardless of the memory size, all devices share the
same rich set of peripherals, allowing for a smooth
migration path as applications grow and evolve.
The consistent pinout scheme used throughout the
entire family also aids in migrating to the next larger
device. This is true when moving between the 64-pin
members, between the 80-pin members, or even
jumping from 64-pin to 80-pin devices.

1.1.4

OTHER SPECIAL FEATURES

� Communications: The PIC18FXX20 family incor-

porates a range of serial communications peripher-
als, including 2 independent USARTs and a Master
SSP module, capable of both SPI and I

C (Master

and Slave) modes of operation. For PIC18F8X20
devices, one of the general purpose I/O ports can be
reconfigured as an 8-bit Parallel Slave Port for direct
processor-to-processor communications.

� CCP Modules: All devices in the family incorporate

5 Capture/Compare/PWM modules to maximize
flexibility in control applications. Up to four different
time-bases may be used to perform several different
operations at once.

� Analog Features: All devices in the family feature

10-bit A/D converters, with up to 16 input channels,
as well as the ability to perform conversions during
SLEEP mode. Also included are dual analog com-
parators with programmable input and output config-
uration, a programmable Low Voltage Detect
module, and a Programmable Brown-out Reset
module.

� Self-programmability: These devices can write to

their own program memory spaces under internal
software control. By using a bootloader routine
located in the protected Boot Block at the top of pro-
gram memory, it becomes possible to create an
application that can update itself in the field.

� PIC18F6520

� PIC18F8520

� PIC18F6620

� PIC18F8620

� PIC18F6720

� PIC18F8720

PIC18FXX20

DS39609A-page 8

Advance Information

2003 Microchip Technology Inc.

1.2

Details on Individual Family
Members

The PIC18FXX20 devices are available in 64-pin and
80-pin packages. They are differentiated from each
other in five ways:
1.

FLASH program memory (32 Kbytes for
PIC18FX520 devices, 64 Kbytes for
PIC18FX620 devices, and 128 Kbytes for
PIC18FX720 devices)

Data RAM (2048 bytes for PIC18FX520
devices, 3840 bytes for PIC18FX620 and
PIC18FX720 devices)

A/D channels (12 for PIC18F6X20 devices,
16 for PIC18F8X20)

I/O pins (52 on PIC18F6X20 devices, 68 on
PIC18F8X20)

External program memory interface (present
only on PIC18F8X20 devices)

All other features for devices in the PIC18FXX20 family
are identical. These are summarized in Table 1-1.
Block diagrams of the PIC18F6X20 and PIC18F8X20
devices are provided in Figure 1-1 and Figure 1-2,
respectively. The pinouts for these device families are
listed in Table 1-2.

TABLE 1-1:

PIC18FXX20 DEVICE FEATURES

Features

PIC18F6520

PIC18F6620

PIC18F6720

PIC18F8520

PIC18F8620

PIC18F8720

Operating Frequency

DC - 40 MHz

DC - 25 MHz

DC - 40 MHz

DC - 25 MHz

Program Memory
(Bytes)

32K

64K

128K

32K

64K

128K

Program Memory
(Instructions)

16384

32768

65536

16384

32768

65536

Data Memory
(Bytes)

2048

3840

2048

3840

Data EEPROM
Memory (Bytes)

1024

External Memory
Interface

Yes

Interrupt Sources

I/O Ports

Ports A, B, C,

D, E, F, G

Ports A, B, C, D,

E, F, G

Ports A, B, C, D,

E, F, G

Ports A, B, C,

D, E, F, G, H, J

Ports A, B, C,

D, E, F, G, H, J

Ports A, B, C,

D, E, F, G, H, J

Timers

Capture/Compare/
PWM Modules

Serial Communications

MSSP,

Addressable

USART (2)

MSSP,

Addressable

USART (2)

MSSP,

Addressable

USART (2)

MSSP,

Addressable

USART (2)

MSSP,

Addressable

USART (2)

MSSP,

Addressable

USART (2)

Parallel Communications

PSP

10-bit Analog-to-Digital
Module

12 input

channels

12 input

channels

12 input

channels

16 input

channels

16 input

channels

16 input

channels

RESETS
(and Delays)

POR, BOR,

RESET

Instruction,

Stack Full,

Stack Underflow

(PWRT, OST)

POR, BOR,

RESET

Instruction,

Stack Full,

Stack Underflow

(PWRT, OST)

POR, BOR,

RESET

Instruction,

Stack Full,

Stack Underflow

(PWRT, OST)

POR, BOR,

RESET

Instruction,

Stack Full,

Stack Underflow

(PWRT, OST)

POR, BOR,

RESET

Instruction,

Stack Full,

Stack Underflow

(PWRT, OST)

POR, BOR,

RESET

Instruction,

Stack Full,

Stack Underflow

(PWRT, OST)

Programmable
Low Voltage Detect

Yes

Programmable
Brown-out Reset

Yes

Instruction Set

77 Instructions

Package

64-pin TQFP

80-pin TQFP

2003 Microchip Technology Inc.

Advance Information

DS39609A-page 11

PIC18FXX20

TABLE 1-2:

PIC18FXX20 PINOUT I/O DESCRIPTIONS

Pin Name

Pin Number

Pin

Type

Buffer

Type

Description

PIC18F6X20 PIC18F8X20

MCLR/V

MCLR

Master Clear (input) or programming
voltage (output).

Master Clear (RESET) input. This pin is
an active low RESET to the device.
Programming voltage input.

OSC1/CLKI

OSC1

CLKI

CMOS/ST

CMOS

Oscillator crystal or external clock input.

Oscillator crystal input or external clock

source input. ST buffer when configured
in RC mode. Otherwise CMOS.

External clock source input. Always

associated with pin function OSC1 (see
OSC1/CLKI, OSC2/CLKO pins).

OSC2/CLKO/RA6

OSC2

CLKO

RA6

I/O

TTL

Oscillator crystal or clock output.

Oscillator crystal output.
Connects to crystal or resonator in
Crystal Oscillator mode.
In RC mode, OSC2 pin outputs CLKO,
which has 1/4 the frequency of OSC1
and denotes the instruction cycle rate.
General purpose I/O pin.

Legend: TTL = TTL compatible input

CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels

Analog = Analog input

= Input

= Output

= Power

= Open Drain (no P diode to V

)

Note 1: Alternate assignment for CCP2 when CCP2MX is not selected (all Operating modes except

Microcontroller).

2: Default assignment when CCP2MX is set.
3: External memory interface functions are only available on PIC18F8X20 devices.
4: CCP2 is multiplexed with this pin by default when configured in Microcontroller mode. Otherwise, it is

multiplexed with either RB3 or RC1.

5: PORTH and PORTJ are only available on PIC18F8X20 (80-pin) devices.
6: AV

must be connected to a positive supply and AV

must be connected to a ground reference for proper

operation of the part in User or ICSP modes. See parameter D001A for details.

PIC18FXX20

DS39609A-page 12

Advance Information

2003 Microchip Technology Inc.

PORTA is a bi-directional I/O port.

RA0/AN0

RA0
AN0

I/O

TTL

Analog

Digital I/O.
Analog input 0.

RA1/AN1

RA1
AN1

I/O

TTL

Analog

Digital I/O.
Analog input 1.

RA2/AN2/V

REF

RA2
AN2
V

REF

I/O

I
I

TTL

Analog
Analog

Digital I/O.
Analog input 2.
A/D reference voltage (Low) input.

RA3/AN3/V

REF

RA3
AN3
V

REF

I/O

I
I

TTL

Analog
Analog

Digital I/O.
Analog input 3.
A/D reference voltage (High) input.

RA4/T0CKI

RA4

T0CKI

I/O

ST/OD

Digital I/O � Open drain when
configured as output.
Timer0 external clock input.

RA5/AN4/LVDIN

RA5
AN4
LVDIN

I/O

I
I

TTL

Analog
Analog

Digital I/O.
Analog input 4.
Low voltage detect input.

RA6

See the OSC2/CLKO/RA6 pin.

TABLE 1-2:

PIC18FXX20 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin Number

Pin

Type

Buffer

Type

Description

PIC18F6X20 PIC18F8X20

Legend: TTL = TTL compatible input

CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels

Analog = Analog input

= Input

= Output

= Power

= Open Drain (no P diode to V

)

Note 1: Alternate assignment for CCP2 when CCP2MX is not selected (all Operating modes except

Microcontroller).

multiplexed with either RB3 or RC1.

5: PORTH and PORTJ are only available on PIC18F8X20 (80-pin) devices.
6: AV

must be connected to a positive supply and AV

must be connected to a ground reference for proper

operation of the part in User or ICSP modes. See parameter D001A for details.

2003 Microchip Technology Inc.

Advance Information

DS39609A-page 13

PIC18FXX20

PORTB is a bi-directional I/O port. PORTB
can be software programmed for internal
weak pull-ups on all inputs.

RB0/INT0

RB0
INT0

I/O

TTL

Digital I/O.
External interrupt 0.

RB1/INT1

RB1
INT1

I/O

TTL

Digital I/O.
External interrupt 1.

RB2/INT2

RB2
INT2

I/O

TTL

Digital I/O.
External interrupt 2.

RB3/INT3/CCP2

RB3
INT3
CCP2

(1)

I/O
I/O
I/O

TTL

ST
ST

Digital I/O.
External interrupt 3.
Capture2 input, Compare2 output,
PWM2 output.

RB4/KBI0

RB4
KBI0

I/O

TTL

Digital I/O.
Interrupt-on-change pin.

RB5/KBI1/PGM

RB5
KBI1
PGM

I/O

TTL

ST
ST

Digital I/O.
Interrupt-on-change pin.
Low voltage ICSP programming enable
pin.

RB6/KBI2/PGC

RB6
KBI2
PGC

I/O

TTL

ST
ST

Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and
ICSP programming clock.

RB7/KBI3/PGD

RB7
KBI3
PGD

I/O
I/O

TTL

Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and
ICSP programming data.

TABLE 1-2:

PIC18FXX20 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin Number

Pin

Type

Buffer

Type

Description

PIC18F6X20 PIC18F8X20

Legend: TTL = TTL compatible input

CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels

Analog = Analog input

= Input

= Output

= Power

= Open Drain (no P diode to V

)

Note 1: Alternate assignment for CCP2 when CCP2MX is not selected (all Operating modes except

Microcontroller).

multiplexed with either RB3 or RC1.

5: PORTH and PORTJ are only available on PIC18F8X20 (80-pin) devices.
6: AV

must be connected to a positive supply and AV

must be connected to a ground reference for proper

operation of the part in User or ICSP modes. See parameter D001A for details.

PIC18FXX20

DS39609A-page 14

Advance Information

2003 Microchip Technology Inc.

PORTC is a bi-directional I/O port.

RC0/T1OSO/T13CKI

RC0
T1OSO
T13CKI

I/O

Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.

RC1/T1OSI/CCP2

RC1
T1OSI
CCP2

(2)

I/O

CMOS

Digital I/O.
Timer1 oscillator input.
Capture2 input/Compare2 output/
PWM2 output.

RC2/CCP1

RC2
CCP1

I/O
I/O

ST
ST

Digital I/O.
Capture1 input/Compare1
output/PWM1 output.

RC3/SCK/SCL

RC3
SCK

SCL

I/O
I/O

I/O

ST
ST

Digital I/O.
Synchronous serial clock
input/output for SPI mode.
Synchronous serial clock
input/output for I

C mode.

RC4/SDI/SDA

RC4
SDI
SDA

I/O

ST
ST
ST

Digital I/O.
SPI data in.
I

C data I/O.

RC5/SDO

RC5
SDO

I/O

Digital I/O.
SPI data out.

RC6/TX1/CK1

RC6
TX1
CK1

I/O

Digital I/O.
USART 1 asynchronous transmit.
USART 1 synchronous clock
(see RX1/DT1).

RC7/RX1/DT1

RC7
RX1
DT1

I/O

ST
ST
ST

Digital I/O.
USART 1 asynchronous receive.
USART 1 synchronous data
(see TX1/CK1).

TABLE 1-2:

PIC18FXX20 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin Number

Pin

Type

Buffer

Type

Description

PIC18F6X20 PIC18F8X20

Legend: TTL = TTL compatible input

CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels

Analog = Analog input

= Input

= Output

= Power

= Open Drain (no P diode to V

)

Note 1: Alternate assignment for CCP2 when CCP2MX is not selected (all Operating modes except

Microcontroller).

multiplexed with either RB3 or RC1.

5: PORTH and PORTJ are only available on PIC18F8X20 (80-pin) devices.
6: AV

must be connected to a positive supply and AV

must be connected to a ground reference for proper

operation of the part in User or ICSP modes. See parameter D001A for details.

2003 Microchip Technology Inc.

Advance Information

DS39609A-page 15

PIC18FXX20

PORTD is a bi-directional I/O port. These
pins have TTL input buffers when external
memory is enabled.

RD0/PSP0/AD0

RD0
PSP0
AD0

(3)

I/O
I/O
I/O

TTL
TTL

Digital I/O.
Parallel Slave Port data.
External memory address/data 0.

RD1/PSP1/AD1

RD1
PSP1
AD1

(3)

I/O
I/O
I/O

TTL
TTL

Digital I/O.
Parallel Slave Port data.
External memory address/data 1.

RD2/PSP2/AD2

RD2
PSP2
AD2

(3)

I/O
I/O
I/O

TTL
TTL

Digital I/O.
Parallel Slave Port data.
External memory address/data 2.

RD3/PSP3/AD3

RD3
PSP3
AD3

(3)

I/O
I/O
I/O

TTL
TTL

Digital I/O.
Parallel Slave Port data.
External memory address/data 3.

RD4/PSP4/AD4

RD4
PSP4
AD4

(3)

I/O
I/O
I/O

TTL
TTL

Digital I/O.
Parallel Slave Port data.
External memory address/data 4.

RD5/PSP5/AD5

RD5
PSP5
AD5

(3)

I/O
I/O
I/O

TTL
TTL

Digital I/O.
Parallel Slave Port data.
External memory address/data 5.

RD6/PSP6/AD6

RD6
PSP6
AD6

(3)

I/O
I/O
I/O

TTL
TTL

Digital I/O.
Parallel Slave Port data.
External memory address/data 6.

RD7/PSP7/AD7

RD7
PSP7
AD7

(3)

I/O
I/O
I/O

TTL
TTL

Digital I/O.
Parallel Slave Port data.
External memory address/data 7.

TABLE 1-2:

PIC18FXX20 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin Number

Pin

Type

Buffer

Type

Description

PIC18F6X20 PIC18F8X20

Legend: TTL = TTL compatible input

CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels

Analog = Analog input

= Input

= Output

= Power

= Open Drain (no P diode to V

)

Note 1: Alternate assignment for CCP2 when CCP2MX is not selected (all Operating modes except

Microcontroller).

multiplexed with either RB3 or RC1.

5: PORTH and PORTJ are only available on PIC18F8X20 (80-pin) devices.
6: AV

must be connected to a positive supply and AV

must be connected to a ground reference for proper

operation of the part in User or ICSP modes. See parameter D001A for details.

PIC18FXX20

DS39609A-page 16

Advance Information

2003 Microchip Technology Inc.

PORTE is a bi-directional I/O port.

RE0/RD/AD8

RE0
RD

AD8

(3)

I/O

TTL

Digital I/O.
Read control for parallel slave port (see
WR and CS pins).
External memory address/data 8.

RE1/WR/AD9

RE1
WR

AD9

(3)

I/O

TTL

Digital I/O.
Write control for parallel slave port (see
CS and RD pins).
External memory address/data 9.

RE2/CS/AD10

RE2
CS

AD10

(3)

I/O

TTL

Digital I/O.
Chip select control for parallel slave port
(see RD and WR).
External memory address/data 10.

RE3/AD11

RE3
AD11

(3)

I/O
I/O

TTL

Digital I/O.
External memory address/data 11.

RE4/AD12

RE4
AD12

I/O
I/O

TTL

Digital I/O.
External memory address/data 12.

RE5/AD13

RE5
AD13

(3)

I/O
I/O

TTL

Digital I/O.
External memory address/data 13.

RE6/AD14

RE6
AD14

(3)

I/O
I/O

TTL

Digital I/O.
External memory address/data 14.

RE7/CCP2/AD15

RE7
CCP2

(1,4)

AD15

(3)

I/O
I/O

I/O

ST
ST

TTL

Digital I/O.
Capture2 input/Compare2 output/
PWM2 output.
External memory address/data 15.

TABLE 1-2:

PIC18FXX20 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin Number

Pin

Type

Buffer

Type

Description

PIC18F6X20 PIC18F8X20

Legend: TTL = TTL compatible input

CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels

Analog = Analog input

= Input

= Output

= Power

= Open Drain (no P diode to V

)

Note 1: Alternate assignment for CCP2 when CCP2MX is not selected (all Operating modes except

Microcontroller).

multiplexed with either RB3 or RC1.

5: PORTH and PORTJ are only available on PIC18F8X20 (80-pin) devices.
6: AV

must be connected to a positive supply and AV

must be connected to a ground reference for proper

operation of the part in User or ICSP modes. See parameter D001A for details.

2003 Microchip Technology Inc.

Advance Information

DS39609A-page 17

PIC18FXX20

PORTF is a bi-directional I/O port.

RF0/AN5

RF0
AN5

I/O

Analog

Digital I/O.
Analog input 5.

RF1/AN6/C2OUT

RF1
AN6
C2OUT

I/O

Analog

Digital I/O.
Analog input 6.
Comparator 2 output.

RF2/AN7/C1OUT

RF2
AN7
C1OUT

I/O

Analog

Digital I/O.
Analog input 7.
Comparator 1 output.

RF3/AN8

RF1
AN8

I/O

Analog

Digital I/O.
Analog input 8.

RF4/AN9

RF1
AN9

I/O

Analog

Digital I/O.
Analog input 9.

RF5/AN10/CV

REF

RF1
AN10
CV

REF

I/O

Analog
Analog

Digital I/O.
Analog input 10.
Comparator V

REF

output.

RF6/AN11

RF6
AN11

I/O

Analog

Digital I/O.
Analog input 11.

RF7/SS

RF7
SS

I/O

TTL

Digital I/O.
SPI slave select input.

TABLE 1-2:

PIC18FXX20 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin Number

Pin

Type

Buffer

Type

Description

PIC18F6X20 PIC18F8X20

Legend: TTL = TTL compatible input

CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels

Analog = Analog input

= Input

= Output

= Power

= Open Drain (no P diode to V

)

Note 1: Alternate assignment for CCP2 when CCP2MX is not selected (all Operating modes except

Microcontroller).

multiplexed with either RB3 or RC1.

5: PORTH and PORTJ are only available on PIC18F8X20 (80-pin) devices.
6: AV

must be connected to a positive supply and AV

must be connected to a ground reference for proper

operation of the part in User or ICSP modes. See parameter D001A for details.

2003 Microchip Technology Inc.

Advance Information

DS39609A-page 19

PIC18FXX20

PORTH is a bi-directional I/O port

(5)

RH0/A16

RH0
A16

I/O

TTL

Digital I/O.
External memory address 16.

RH1/A17

RH1
A17

I/O

TTL

Digital I/O.
External memory address 17.

RH2/A18

RH2
A18

I/O

TTL

Digital I/O.
External memory address 18.

RH3/A19

RH3
A19

I/O

TTL

Digital I/O.
External memory address 19.

RH4/AN12

RH4
AN12

I/O

Analog

Digital I/O.
Analog input 12.

RH5/AN13

RH5
AN13

I/O

Analog

Digital I/O.
Analog input 13.

RH6/AN14

RH6
AN14

I/O

Analog

Digital I/O.
Analog input 14.

RH7/AN15

RH7
AN15

I/O

Analog

Digital I/O.
Analog input 15.

TABLE 1-2:

PIC18FXX20 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin Number

Pin

Type

Buffer

Type

Description

PIC18F6X20 PIC18F8X20

Legend: TTL = TTL compatible input

CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels

Analog = Analog input

= Input

= Output

= Power

= Open Drain (no P diode to V

)

Note 1: Alternate assignment for CCP2 when CCP2MX is not selected (all Operating modes except

Microcontroller).

multiplexed with either RB3 or RC1.

5: PORTH and PORTJ are only available on PIC18F8X20 (80-pin) devices.
6: AV

must be connected to a positive supply and AV

must be connected to a ground reference for proper

operation of the part in User or ICSP modes. See parameter D001A for details.

PIC18FXX20

DS39609A-page 20

Advance Information

2003 Microchip Technology Inc.

PORTJ is a bi-directional I/O port

(5)

RJ0/ALE

RJ0
ALE

I/O

TTL

Digital I/O.
External memory Address Latch Enable.

RJ1/OE

RJ1
OE

I/O

TTL

Digital I/O.
External memory Output Enable.

RJ2/WRL

RJ2
WRL

I/O

TTL

Digital I/O.
External memory Write Low control.

RJ3/WRH

RJ3
WRH

I/O

TTL

Digital I/O.
External memory Write High control.

RJ4/BA0

RJ4
BA0

I/O

TTL

Digital I/O.
External memory Byte Address 0 control.

RJ5/CE

RJ5
CE

I/O

TTL

Digital I/O.
External memory Chip Enable control.

RJ6/LB

RJ6
LB

I/O

TTL

Digital I/O.
External memory Low Byte select.

RJ7/UB

RJ7
UB

I/O

TTL

Digital I/O.
External memory High Byte select.

9, 25,

41, 56

11, 31,

51, 70

Ground reference for logic and I/O pins.

10, 26,

38, 57

12, 32,

48, 71

Positive supply for logic and I/O pins.

SS(6)

Ground reference for analog modules.

DD(6)

Positive supply for analog modules.

TABLE 1-2:

PIC18FXX20 PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name

Pin Number

Pin

Type

Buffer

Type

Description

PIC18F6X20 PIC18F8X20

Legend: TTL = TTL compatible input

CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels

Analog = Analog input

= Input

= Output

= Power

= Open Drain (no P diode to V

)

Note 1: Alternate assignment for CCP2 when CCP2MX is not selected (all Operating modes except

Microcontroller).

multiplexed with either RB3 or RC1.

5: PORTH and PORTJ are only available on PIC18F8X20 (80-pin) devices.
6: AV

must be connected to a positive supply and AV

must be connected to a ground reference for proper

operation of the part in User or ICSP modes. See parameter D001A for details.

2003 Microchip Technology Inc.

Advance Information

DS39609A-page 21

PIC18FXX20

2.0

OSCILLATOR
CONFIGURATIONS

2.1

Oscillator Types

The PIC18FXX20 devices can be operated in eight dif-
ferent Oscillator modes. The user can program three
configuration bits (FOSC2, FOSC1, and FOSC0) to
select one of these eight modes:
1.

Low Power Crystal

Crystal/Resonator

High Speed Crystal/Resonator

HS+PLL

High Speed Crystal/Resonator
with PLL enabled

External Resistor/Capacitor

RCIO

External Resistor/Capacitor with

I/O pin enabled

External Clock

ECIO

External Clock with I/O pin
enabled

2.2

Crystal Oscillator/Ceramic
Resonators

In XT, LP, HS or HS+PLL Oscillator modes, a crystal or
ceramic resonator is connected to the OSC1 and
OSC2 pins to establish oscillation. Figure 2-1 shows
the pin connections.
The PIC18FXX20 oscillator design requires the use of
a parallel cut crystal.

FIGURE 2-1:

CRYSTAL/CERAMIC
RESONATOR OPERATION
(HS, XT OR LP
CONFIGURATION)

TABLE 2-1:

CAPACITOR SELECTION FOR
CERAMIC RESONATORS

Note:

Use of a series cut crystal may give a fre-
quency out of the crystal manufacturer's
specifications.

Note 1: See Table 2-1 and Table 2-2 for recommended

values of C1 and C2.

2: A series resistor (R

) may be required for AT

strip cut crystals.

3: R

varies with the Oscillator mode chosen.

(1)

XTAL

OSC2

OSC1

(3)

SLEEP

Logic

PIC18FXX20

S(2)

Internal

Ranges Tested:

Mode

Freq

455 kHz

2.0 MHz
4.0 MHz

68 - 100 pF

15 - 68 pF
15 - 68 pF

68 - 100 pF

15 - 68 pF
15 - 68 pF

8.0 MHz

16.0 MHz

10 - 68 pF
10 - 22 pF

These values are for design guidance only.
See notes following this table.

Resonators Used:

455 kHz Panasonic EFO-A455K04B

� 0.3%

2.0 MHz Murata Erie CSA2.00MG

� 0.5%

4.0 MHz Murata Erie CSA4.00MG

� 0.5%

8.0 MHz Murata Erie CSA8.00MT

� 0.5%

16.0 MHz Murata Erie CSA16.00MX

� 0.5%

All resonators used did not have built-in capacitors.

Note 1: Higher capacitance increases the stability

of the oscillator, but also increases the
start-up time.

2: When operating below 3V V

, or when

using certain ceramic resonators at any
voltage, it may be necessary to use high
gain HS mode, try a lower frequency
resonator, or switch to a crystal oscillator.

3: Since each resonator/crystal has its own

characteristics, the user should consult the
resonator/crystal manufacturer for appro-
priate values of external components, or
verify oscillator performance.

PIC18FXX20

DS39609A-page 22

Advance Information

2003 Microchip Technology Inc.

TABLE 2-2:

CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR

An external clock source may also be connected to the
OSC1 pin in the HS, XT and LP modes, as shown in
Figure 2-2.

FIGURE 2-2:

EXTERNAL CLOCK INPUT
OPERATION (HS, XT OR
LP OSC
CONFIGURATION)

2.3

RC Oscillator

For timing insensitive applications, the "RC" and
"RCIO" device options offer additional cost savings.
The RC oscillator frequency is a function of the supply
voltage, the resistor (R

EXT

) and capacitor (C

EXT

) val-

ues and the operating temperature. In addition to this,
the oscillator frequency will vary from unit to unit, due
to normal process parameter variation. Furthermore,
the difference in lead frame capacitance between pack-
age types will also affect the oscillation frequency,
especially for low C

EXT

values. The user also needs to

take into account variation due to tolerance of external
R and C components used. Figure 2-3 shows how the
R/C combination is connected.
In the RC Oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal
may be used for test purposes or to synchronize other
logic.

FIGURE 2-3:

RC OSCILLATOR MODE

The RCIO Oscillator mode functions like the RC mode,
except that the OSC2 pin becomes an additional gen-
eral purpose I/O pin. The I/O pin becomes bit 6 of
PORTA (RA6).

Ranges Tested:

Mode

Freq

32.0 kHz

33 pF

200 kHz

15 pF

200 kHz

47-68 pF

1.0 MHz

15 pF

4.0 MHz

15 pF

4.0 MHz

15 pF

8.0 MHz

15-33 pF

20.0

MHz

15-33 pF

25.0

MHz

TBD

These values are for design guidance only.
See notes following this table.

Crystals Used

32.0 kHz

Epson C-001R32.768K-A

� 20 PPM

200 kHz

STD XTL 200.000KHz

� 20 PPM

1.0 MHz

ECS ECS-10-13-1

� 50 PPM

4.0 MHz

ECS ECS-40-20-1

� 50 PPM

8.0 MHz

Epson CA-301 8.000M-C

� 30 PPM

20.0 MHz

Epson CA-301 20.000M-C � 30 PPM

Note 1: Higher capacitance increases the stability

of the oscillator, but also increases the
start-up time.

2: Rs (see Figure 2-1) may be required in

HS mode, as well as XT mode, to avoid
overdriving crystals with low drive level
specification.

3: Since each resonator/crystal has its own

characteristics, the user should consult the
resonator/crystal manufacturer for appro-
priate values of external components, or
verify oscillator performance.

OSC1

OSC2

Open

Clock from
Ext. System

PIC18FXX20

OSC2/CLKO

EXT

PIC18FXX20

OSC1

OSC

Internal

Clock

Recommended values:

3 k

EXT

100 k

EXT

> 20 pF

2003 Microchip Technology Inc.

Advance Information

DS39609A-page 23

PIC18FXX20

2.4

External Clock Input

The EC and ECIO Oscillator modes require an external
clock source to be connected to the OSC1 pin. The
feedback device between OSC1 and OSC2 is turned
off in these modes to save current. There is a maximum
1.5

祍 start-up required after a Power-on Reset, or

wake-up from SLEEP mode.
In the EC Oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal
may be used for test purposes or to synchronize other
logic. Figure 2-4 shows the pin connections for the EC
Oscillator mode.

FIGURE 2-4:

EXTERNAL CLOCK INPUT
OPERATION
(EC CONFIGURATION)

The ECIO Oscillator mode functions like the EC mode,
except that the OSC2 pin becomes an additional gen-
eral purpose I/O pin. The I/O pin becomes bit 6 of
PORTA (RA6). Figure 2-5 shows the pin connections
for the ECIO Oscillator mode.

FIGURE 2-5:

EXTERNAL CLOCK INPUT
OPERATION
(ECIO CONFIGURATION)

2.5

HS/PLL

A Phase Locked Loop circuit (PLL) is provided as a
programmable option for users that want to multiply the
frequency of the incoming crystal oscillator signal by 4.
For an input clock frequency of 10 MHz, the internal
clock frequency will be multiplied to 40 MHz. This is
useful for customers who are concerned with EMI due
to high frequency crystals.
The PLL is one of the modes of the FOSC<2:0> config-
uration bits. The Oscillator mode is specified during
device programming.
The PLL can only be enabled when the oscillator con-
figuration bits are programmed for HS mode. If they are
programmed for any other mode, the PLL is not
enabled and the system clock will come directly from
OSC1. Also, PLL operation cannot be changed
"on-the-fly". To enable or disable it, the controller must
either cycle through a Power-on Reset, or switch the
clock source from the main oscillator to the Timer1
oscillator and back again. (See Section 2.6 for details
on Oscillator Switching.)
A PLL lock timer is used to ensure that the PLL has
locked before device execution starts. The PLL lock
timer has a time-out that is called T

PLL

FIGURE 2-6:

PLL BLOCK DIAGRAM

OSC1

OSC2

OSC

Clock from
Ext. System

PIC18FXX20

OSC1

I/O (OSC2)

RA6

Clock from
Ext. System

PIC18FXX20

MUX

VCO

Loop
Filter

Divide by 4

Crystal

Osc

OSC2

OSC1

PLL Enable

OUT

SYSCLK

Phase

Comparator

(from Configuration

HS Osc

bit Register)

PIC18FXX20

DS39609A-page 26

Advance Information

2003 Microchip Technology Inc.

2.6.2

OSCILLATOR TRANSITIONS

PIC18FXX20 devices contain circuitry to prevent
"glitches" when switching between oscillator sources.
Essentially, the circuitry waits for eight rising edges of
the clock source that the processor is switching to. This
ensures that the new clock source is stable and that its
pulse width will not be less than the shortest pulse
width of the two clock sources.

A timing diagram indicating the transition from the main
oscillator to the Timer1 oscillator is shown in
Figure 2-8. The Timer1 oscillator is assumed to be run-
ning all the time. After the SCS bit is set, the processor
is frozen at the next occurring Q1 cycle. After eight syn-
chronization cycles are counted from the Timer1 oscil-
lator, operation resumes. No additional delays are
required after the synchronization cycles.

FIGURE 2-8:

TIMING DIAGRAM FOR TRANSITION FROM OSC1 TO TIMER1 OSCILLATOR

The sequence of events that takes place when switch-
ing from the Timer1 oscillator to the main oscillator will
depend on the mode of the main oscillator. In addition
to eight clock cycles of the main oscillator, additional
delays may take place.

If the main oscillator is configured for an external crys-
tal (HS, XT, LP), then the transition will take place after
an oscillator start-up time (T

OST

) has occurred. A timing

diagram, indicating the transition from the Timer1 oscil-
lator to the main oscillator for HS, XT and LP modes, is
shown in Figure 2-9.

FIGURE 2-9:

TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (HS, XT, LP)

OSC1

Internal

SCS

(OSCCON<0>)
Program

PC + 2

Note 1: Delay on internal system clock is eight oscillator cycles for synchronization.

T1OSI

PC + 4

SCS

Clock

Counter

System

DLY

OSC

Q2 Q3

Q1 Q2

OSC1

Internal

SCS

(OSCCON<0>)

Program

PC + 2

Note 1: T

OST

= 1024 T

OSC

(drawing not to scale).

T1OSI

System Clock

OSC2

OST

PC + 6

OSC

SCS

Counter

PIC18FXX20

DS39609A-page 28

Advance Information

2003 Microchip Technology Inc.

2.7

Effects of SLEEP Mode on the
On-Chip Oscillator

When the device executes a SLEEP instruction, the
on-chip clocks and oscillator are turned off and the
device is held at the beginning of an instruction cycle
(Q1 state). With the oscillator off, the OSC1 and OSC2
signals will stop oscillating. Since all the transistor

switching currents have been removed, SLEEP mode
achieves the lowest current consumption of the device
(only leakage currents). Enabling any on-chip feature
that will operate during SLEEP, will increase the current
consumed during SLEEP. The user can wake from
SLEEP through external RESET, Watchdog Timer
Reset, or through an interrupt.

TABLE 2-3:

OSC1 AND OSC2 PIN STATES IN SLEEP MODE

2.8

Power-up Delays

Power up delays are controlled by two timers, so that
no external RESET circuitry is required for most appli-
cations. The delays ensure that the device is kept in
RESET until the device power supply and clock are sta-
ble. For additional information on RESET operation,
see the "Reset" section.
The first timer is the Power-up Timer (PWRT), which
optionally provides a fixed delay of 72 ms (nominal) on
power-up only (POR and BOR). The second timer is
the Oscillator Start-up Timer (OST), intended to keep
the chip in RESET until the crystal oscillator is stable.

With the PLL enabled (HS/PLL Oscillator mode), the
time-out sequence following a Power-on Reset is differ-
ent from other Oscillator modes. The time-out
sequence is as follows: First, the PWRT time-out is
invoked after a POR time delay has expired. Then, the
Oscillator Start-up Timer (OST) is invoked. However,
this is still not a sufficient amount of time to allow the
PLL to lock at high frequencies. The PWRT timer is
used to provide an additional fixed 2 ms (nominal)
time-out to allow the PLL ample time to lock to the
incoming clock frequency.

OSC Mode

OSC1 Pin

OSC2 Pin

Floating, external resistor should pull high

At logic low

RCIO

Floating, external resistor should pull high

Configured as PORTA, bit 6

ECIO

Floating

Configured as PORTA, bit 6

Floating

At logic low

LP, XT, and HS

Feedback inverter disabled, at quiescent

voltage level

Feedback inverter disabled, at quiescent

voltage level

Note:

See Table 3-1 in the "Reset" section, for time-outs due to SLEEP and MCLR Reset.

2003 Microchip Technology Inc.

Advance Information

DS39609A-page 29

PIC18FXX20

3.0

RESET

The PIC18FXX20 devices differentiate between
various kinds of RESET:
a)

Power-on Reset (POR)

MCLR Reset during normal operation

MCLR Reset during SLEEP

Watchdog Timer (WDT) Reset (during normal
operation)

Programmable Brown-out Reset (PBOR)

RESET

Instruction

Stack Full Reset

Stack Underflow Reset

Most registers are unaffected by a RESET. Their status
is unknown on POR and unchanged by all other
RESETS. The other registers are forced to a "RESET

state" on Power-on Reset, MCLR, WDT Reset,
Brown-out Reset, MCLR Reset during SLEEP and by
the RESET instruction.
Most registers are not affected by a WDT wake-up,
since this is viewed as the resumption of normal oper-
ation. Status bits from the RCON register, RI, TO, PD,
POR and BOR, are set or cleared differently in different
RESET situations, as indicated in Table 3-2. These bits
are used in software to determine the nature of the
RESET. See Table 3-3 for a full description of the
RESET states of all registers.
A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 3-1.
The Enhanced MCU devices have a MCLR noise filter
in the MCLR Reset path. The filter will detect and
ignore small pulses. The MCLR pin is not driven low by
any internal RESETS, including the WDT.

FIGURE 3-1:

SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

External Reset

MCLR

OSC1

WDT

Module

Rise

Detect

OST/PWRT

On-chip

RC OSC

(1)

WDT

Time-out

Power-on Reset

OST

10-bit Ripple Counter

PWRT

Chip_Reset

10-bit Ripple Counter

Reset

Enable OST

(2)

Enable PWRT

SLEEP

Note 1: This is a separate oscillator from the RC oscillator of the CLKI pin.

2: See Table 3-1 for time-out situations.

Brown-out

Reset

BOREN

RESET

Instruction

Stack

Pointer

Stack Full/Underflow Reset

PIC18FXX20

DS39609A-page 30

Advance Information

2003 Microchip Technology Inc.

3.1

Power-on Reset (POR)

A Power-on Reset pulse is generated on-chip when
V

rise is detected. To take advantage of the POR cir-

cuitry, tie the MCLR pin through a 1 k

to 10 k resis-

tor to V

. This will eliminate external RC components

usually needed to create a Power-on Reset delay. A
minimum rise rate for V

is specified (parameter

D004). For a slow rise time, see Figure 3-2.
When the device starts normal operation (i.e., exits the
RESET condition), device operating parameters (volt-
age, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in RESET until the operating
conditions are met.

FIGURE 3-2:

EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW V

POWER-UP)

3.2

Power-up Timer (PWRT)

The Power-up Timer provides a fixed nominal time-out
(parameter #33) only on power-up from the POR. The
Power-up Timer operates on an internal RC oscillator.
The chip is kept in RESET as long as the PWRT is
active. The PWRT's time delay allows V

to rise to an

acceptable level. A configuration bit is provided to
enable/disable the PWRT.
The power-up time delay will vary from chip-to-chip due
to V

, temperature and process variation. See DC

parameter #33 for details.

3.3

Oscillator Start-up Timer (OST)

The Oscillator Start-up Timer (OST) provides 1024
oscillator cycle (from OSC1 input) delay after the
PWRT delay is over (parameter #32). This ensures that
the crystal oscillator or resonator has started and
stabilized.
The OST time-out is invoked only for XT, LP and HS
modes and only on Power-on Reset, or wake-up from
SLEEP.

3.4

PLL Lock Time-out

With the PLL enabled, the time-out sequence following
a Power-on Reset is different from other oscillator
modes. A portion of the Power-up Timer is used to pro-
vide a fixed time-out that is sufficient for the PLL to lock
to the main oscillator frequency. This PLL lock time-out
(T

PLL

) is typically 2 ms and follows the oscillator

start-up time-out (OST).

3.5

Brown-out Reset (BOR)

A configuration bit, BOREN, can disable (if
clear/programmed), or enable (if set) the Brown-out
Reset circuitry. If V

falls below parameter D005 for

greater than parameter #35, the brown-out situation will
reset the chip. A RESET may not occur if V

falls

below parameter D005 for less than parameter #35.
The chip will remain in Brown-out Reset until V

rises

above BV

. If the Power-up Timer is enabled, it will be

invoked after V

rises above BV

; it then will keep

the chip in RESET for an additional time delay (param-
eter #33). If V

drops below BV

while the Power-up

Timer is running, the chip will go back into a Brown-out
Reset and the Power-up Timer will be initialized. Once
V

rises above BV

, the Power-up Timer will

execute the additional time delay.

3.6

Time-out Sequence

On power-up, the time-out sequence is as follows:
First, PWRT time-out is invoked after the POR time
delay has expired. Then, OST is activated. The total
time-out will vary based on oscillator configuration and
the status of the PWRT. For example, in RC mode with
the PWRT disabled, there will be no time-out at all.
Figure 3-3, Figure 3-4, Figure 3-5, Figure 3-6 and
Figure 3-7 depict time-out sequences on power-up.
Since the time-outs occur from the POR pulse, the
time-outs will expire if MCLR is kept low long enough.
Bringing MCLR high will begin execution immediately
(Figure 3-5). This is useful for testing purposes, or to
synchronize more than one PIC18FXX20 device
operating in parallel.
Table 3-2 shows the RESET conditions for some
Special Function Registers, while Table 3-3 shows the
RESET conditions for all of the registers.

Note 1: External Power-on Reset circuit is required

only if the V

power-up slope is too slow.

The diode D helps discharge the capacitor
quickly when V

powers down.

2: R < 40 k

is recommended to make sure that

the voltage drop across R does not violate
the device's electrical specification.

3: R1 = 1 k

to 10 k will limit any current flow-

ing into MCLR from external capacitor C, in
the event of MCLR/V

pin breakdown due to

Electrostatic Discharge (ESD), or Electrical
Overstress (EOS).

MCLR

PIC18FXX20

2003 Microchip Technology Inc.

Advance Information

DS39609A-page 31

PIC18FXX20

TABLE 3-1:

TIME-OUT IN VARIOUS SITUATIONS

REGISTER 3-1:

RCON REGISTER BITS AND POSITIONS

TABLE 3-2:

STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR
RCON REGISTER

Oscillator

Configuration

Power-up

(2)

Brown-out

Wake-up from

SLEEP or

Oscillator Switch

PWRTE = 0

PWRTE = 1

HS with PLL enabled

(1)

72 ms + 1024 T

OSC

+ 2ms

1024 T

OSC

+ 2 ms

72 ms

(2)

+ 1024 T

OSC

+ 2 ms

1024 T

OSC

+ 2 ms

HS, XT, LP

72 ms + 1024 T

OSC

1024 T

OSC

72 ms

(2)

+ 1024 T

OSC

1024 T

OSC

72 ms

1.5

祍

72 ms

(2)

1.5

祍

(3)

External RC

72 ms

(2)

Note 1: 2 ms is the nominal time required for the 4xPLL to lock.

2: 72 ms is the nominal power-up timer delay, if implemented.
3: 1.5

祍 is the recovery time from SLEEP. There is no recovery time from oscillator switch.

R/W-0

U-0

R/W-1

IPEN

POR

BOR

bit 7

bit 0

Note 1: Refer to Section 4.14 (page 60) for bit definitions.

Condition

Program

Counter

RCON

Register

POR

BOR

STKFUL

STKUNF

Power-on Reset

0000h

0--1 1100

MCLR Reset during normal
operation

0000h

0--u uuuu

Software Reset during normal
operation

0000h

0--0 uuuu

Stack Full Reset during normal
operation

0000h

0--u uu11

Stack Underflow Reset during
normal operation

0000h

0--u uu11

MCLR Reset during SLEEP

0000h

0--u 10uu

WDT Reset

0000h

0--u 01uu

WDT Wake-up

PC + 2

u--u 00uu

Brown-out Reset

0000h

0--1 11u0

Interrupt wake-up from SLEEP

PC + 2

(1)

u--u 00uu

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0'
Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the

interrupt vector (0x000008h or 0x000018h).

PIC18FXX20

DS39609A-page 32

Advance Information

2003 Microchip Technology Inc.

TABLE 3-3:

INITIALIZATION CONDITIONS FOR ALL REGISTERS

Register

Applicable Devices

Power-on Reset,

Brown-out Reset

MCLR Resets

WDT Reset

RESET

Instruction

Stack Resets

Wake-up via WDT

or Interrupt

TOSU

PIC18F6X20 PIC18F8X20

---0 0000

---0 uuuu

(3)

TOSH

PIC18F6X20 PIC18F8X20

0000 0000

uuuu uuuu

(3)

TOSL

PIC18F6X20 PIC18F8X20

0000 0000

uuuu uuuu

(3)

STKPTR

PIC18F6X20 PIC18F8X20

00-0 0000

uu-0 0000

uu-u uuuu

(3)

PCLATU

PIC18F6X20 PIC18F8X20

---0 0000

---u uuuu

PCLATH

PIC18F6X20 PIC18F8X20

0000 0000

uuuu uuuu

PCL

PIC18F6X20 PIC18F8X20

0000 0000

PC + 2

(2)

TBLPTRU

PIC18F6X20 PIC18F8X20

--00 0000

--uu uuuu

TBLPTRH

PIC18F6X20 PIC18F8X20

0000 0000

uuuu uuuu

TBLPTRL

PIC18F6X20 PIC18F8X20

0000 0000

uuuu uuuu

TABLAT

PIC18F6X20 PIC18F8X20

0000 0000

uuuu uuuu

PRODH

PIC18F6X20 PIC18F8X20

xxxx xxxx

uuuu uuuu

PRODL

PIC18F6X20 PIC18F8X20

xxxx xxxx

uuuu uuuu

INTCON

PIC18F6X20 PIC18F8X20

0000 0000

uuuu uuuu

(1)

INTCON2

PIC18F6X20 PIC18F8X20

1111 1111

uuuu uuuu

(1)

INTCON3

PIC18F6X20 PIC18F8X20

1100 0000

uuuu uuuu

(1)

INDF0

PIC18F6X20 PIC18F8X20

N/A

POSTINC0

PIC18F6X20 PIC18F8X20

N/A

POSTDEC0 PIC18F6X20 PIC18F8X20

N/A

PREINC0

PIC18F6X20 PIC18F8X20

N/A

PLUSW0

PIC18F6X20 PIC18F8X20

N/A

FSR0H

PIC18F6X20 PIC18F8X20

---- xxxx

---- uuuu

FSR0L

PIC18F6X20 PIC18F8X20

xxxx xxxx

uuuu uuuu

WREG

PIC18F6X20 PIC18F8X20

xxxx xxxx

uuuu uuuu

INDF1

PIC18F6X20 PIC18F8X20

N/A

POSTINC1

PIC18F6X20 PIC18F8X20

N/A

POSTDEC1 PIC18F6X20 PIC18F8X20

N/A

PREINC1

PIC18F6X20 PIC18F8X20

N/A

PLUSW1

PIC18F6X20 PIC18F8X20

N/A

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt

vector (0008h or 0018h).

3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.

4: See Table 3-2 for RESET value for specific condition.
5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other

Oscillator modes, they are disabled and read `0'.

6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read `0'.

2003 Microchip Technology Inc.

Advance Information

DS39609A-page 33

PIC18FXX20

FSR1H

PIC18F6X20 PIC18F8X20

---- xxxx

---- uuuu

FSR1L

PIC18F6X20 PIC18F8X20

xxxx xxxx

uuuu uuuu

BSR

PIC18F6X20 PIC18F8X20

---- 0000

---- uuuu

INDF2

PIC18F6X20 PIC18F8X20

N/A

POSTINC2

PIC18F6X20 PIC18F8X20

N/A

POSTDEC2 PIC18F6X20 PIC18F8X20

N/A

PREINC2

PIC18F6X20 PIC18F8X20

N/A

PLUSW2

PIC18F6X20 PIC18F8X20

N/A

FSR2H

PIC18F6X20 PIC18F8X20

---- xxxx

---- uuuu

FSR2L

PIC18F6X20 PIC18F8X20

xxxx xxxx

uuuu uuuu

STATUS

PIC18F6X20 PIC18F8X20

---x xxxx

---u uuuu

TMR0H

PIC18F6X20 PIC18F8X20

0000 0000

uuuu uuuu

TMR0L

PIC18F6X20 PIC18F8X20

xxxx xxxx

uuuu uuuu

T0CON

PIC18F6X20 PIC18F8X20

1111 1111

uuuu uuuu

OSCCON

PIC18F6X20 PIC18F8X20

---- ---0

---- ---u

LVDCON

PIC18F6X20 PIC18F8X20

--00 0101

--uu uuuu

WDTCON

PIC18F6X20 PIC18F8X20

---- ---0

---- ---u

RCON

(4)

PIC18F6X20 PIC18F8X20

0--q 11qq

0--q qquu

u--u qquu

TMR1H

PIC18F6X20 PIC18F8X20

xxxx xxxx

uuuu uuuu

TMR1L

PIC18F6X20 PIC18F8X20

xxxx xxxx

uuuu uuuu

T1CON

PIC18F6X20 PIC18F8X20

0-00 0000

u-uu uuuu

TMR2

PIC18F6X20 PIC18F8X20

0000 0000

uuuu uuuu

PR2

PIC18F6X20 PIC18F8X20

1111 1111

T2CON

PIC18F6X20 PIC18F8X20

-000 0000

-uuu uuuu

SSPBUF

PIC18F6X20 PIC18F8X20

xxxx xxxx

uuuu uuuu

SSPADD

PIC18F6X20 PIC18F8X20

0000 0000

uuuu uuuu

SSPSTAT

PIC18F6X20 PIC18F8X20

0000 0000

uuuu uuuu

SSPCON1

PIC18F6X20 PIC18F8X20

0000 0000

uuuu uuuu

SSPCON2

PIC18F6X20 PIC18F8X20

0000 0000

uuuu uuuu

TABLE 3-3:

INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

Register

Applicable Devices

Power-on Reset,

Brown-out Reset

MCLR Resets

WDT Reset

RESET

Instruction

Stack Resets

Wake-up via WDT

or Interrupt

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt

vector (0008h or 0018h).

3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.

4: See Table 3-2 for RESET value for specific condition.
5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other

Oscillator modes, they are disabled and read `0'.

6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read `0'.

PIC18FXX20

DS39609A-page 34

Advance Information

2003 Microchip Technology Inc.

ADRESH

PIC18F6X20 PIC18F8X20

xxxx xxxx

uuuu uuuu

ADRESL

PIC18F6X20 PIC18F8X20

xxxx xxxx

uuuu uuuu

ADCON0

PIC18F6X20 PIC18F8X20

--00 0000

--uu uuuu

ADCON1

PIC18F6X20 PIC18F8X20

--00 0000

--uu uuuu

ADCON2

PIC18F6X20 PIC18F8X20

0--- -000

u--- -uuu

CCPR1H

PIC18F6X20 PIC18F8X20

xxxx xxxx

uuuu uuuu

CCPR1L

PIC18F6X20 PIC18F8X20

xxxx xxxx

uuuu uuuu

CCP1CON

PIC18F6X20 PIC18F8X20

--00 0000

--uu uuuu

CCPR2H

PIC18F6X20 PIC18F8X20

xxxx xxxx

uuuu uuuu

CCPR2L

PIC18F6X20 PIC18F8X20

xxxx xxxx

uuuu uuuu

CCP2CON

PIC18F6X20 PIC18F8X20

--00 0000

--uu uuuu

CCPR3H

PIC18F6X20 PIC18F8X20

xxxx xxxx

uuuu uuuu

CCPR3L

PIC18F6X20 PIC18F8X20

xxxx xxxx

uuuu uuuu

CCP3CON

PIC18F6X20 PIC18F8X20

0000 0000

uuuu uuuu

CVRCON

PIC18F6X20 PIC18F8X20

0000 0000

uuuu uuuu

CMCON

PIC18F6X20 PIC18F8X20

0000 0000

uuuu uuuu

TMR3H

PIC18F6X20 PIC18F8X20

xxxx xxxx

uuuu uuuu

TMR3L

PIC18F6X20 PIC18F8X20

xxxx xxxx

uuuu uuuu

T3CON

PIC18F6X20 PIC18F8X20

0000 0000

uuuu uuuu

PSPCON

PIC18F6X20 PIC18F8X20

0000 ----

uuuu ----

SPBRG1

PIC18F6X20 PIC18F8X20

0000 0000

uuuu uuuu

RCREG1

PIC18F6X20 PIC18F8X20

0000 0000

uuuu uuuu

TXREG1

PIC18F6X20 PIC18F8X20

0000 0000

uuuu uuuu

TXSTA1

PIC18F6X20 PIC18F8X20

0000 -010

uuuu -uuu

RCSTA1

PIC18F6X20 PIC18F8X20

0000 000x

uuuu uuuu

EEADRH

PIC18F6X20 PIC18F8X20

---- --00

---- --uu

EEADR

PIC18F6X20 PIC18F8X20

0000 0000

uuuu uuuu

EEDATA

PIC18F6X20 PIC18F8X20

0000 0000

uuuu uuuu

EECON2

PIC18F6X20 PIC18F8X20

xx-0 x000

uu-0 u000

EECON1

PIC18F6X20 PIC18F8X20

---- ----

TABLE 3-3:

INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

Register

Applicable Devices

Power-on Reset,

Brown-out Reset

MCLR Resets

WDT Reset

RESET

Instruction

Stack Resets

Wake-up via WDT

or Interrupt

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt

vector (0008h or 0018h).

3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.

4: See Table 3-2 for RESET value for specific condition.
5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other

Oscillator modes, they are disabled and read `0'.

6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read `0'.

2003 Microchip Technology Inc.

Advance Information

DS39609A-page 35

PIC18FXX20

IPR3

PIC18F6X20 PIC18F8X20

--11 1111

--uu uuuu

PIR3

PIC18F6X20 PIC18F8X20

--00 0000

--uu uuuu

PIE3

PIC18F6X20 PIC18F8X20

--00 0000

--uu uuuu

IPR2

PIC18F6X20 PIC18F8X20

-1-1 1111

-u-u uuuu

PIR2

PIC18F6X20 PIC18F8X20

-0-0 0000

-u-u uuuu

(1)

PIE2

PIC18F6X20 PIC18F8X20

-0-0 0000

-u-u uuuu

IPR1

PIC18F6X20 PIC18F8X20

0111 1111

uuuu uuuu

PIR1

PIC18F6X20 PIC18F8X20

0000 0000

uuuu uuuu

(1)

PIE1

PIC18F6X20 PIC18F8X20

0000 0000

uuuu uuuu

MEMCON

PIC18F6X20 PIC18F8X20

0-00 --00

u-uu --uu

TRISJ

PIC18F6X20 PIC18F8X20

1111 1111

uuuu uuuu

TRISH

PIC18F6X20 PIC18F8X20

1111 1111

uuuu uuuu

TRISG

PIC18F6X20 PIC18F8X20

---1 1111

---u uuuu

TRISF

PIC18F6X20 PIC18F8X20

1111 1111

uuuu uuuu

TRISE

PIC18F6X20 PIC18F8X20

0000 -111

uuuu -uuu

TRISD

PIC18F6X20 PIC18F8X20

1111 1111

uuuu uuuu

TRISC

PIC18F6X20 PIC18F8X20

1111 1111

uuuu uuuu

TRISB

PIC18F6X20 PIC18F8X20

1111 1111

uuuu uuuu

TRISA

(5,6)

PIC18F6X20 PIC18F8X20

-111 1111

(5)

-111 1111

(5)

-uuu uuuu

(5)

LATJ

PIC18F6X20 PIC18F8X20

xxxx xxxx

uuuu uuuu

LATH

PIC18F6X20 PIC18F8X20

xxxx xxxx

uuuu uuuu

LATG

PIC18F6X20 PIC18F8X20

---x xxxx

---u uuuu

LATF

PIC18F6X20 PIC18F8X20

xxxx xxxx

uuuu uuuu

LATE

PIC18F6X20 PIC18F8X20

xxxx xxxx

uuuu uuuu

LATD

PIC18F6X20 PIC18F8X20

xxxx xxxx

uuuu uuuu

LATC

PIC18F6X20 PIC18F8X20

xxxx xxxx

uuuu uuuu

LATB

PIC18F6X20 PIC18F8X20

xxxx xxxx

uuuu uuuu

LATA

(5,6)

PIC18F6X20 PIC18F8X20

-xxx xxxx

(5)

-uuu uuuu

(5)

-uuu uuuu

(5)

TABLE 3-3:

INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

Register

Applicable Devices

Power-on Reset,

Brown-out Reset

MCLR Resets

WDT Reset

RESET

Instruction

Stack Resets

Wake-up via WDT

or Interrupt

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt

vector (0008h or 0018h).

3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.

4: See Table 3-2 for RESET value for specific condition.
5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other

Oscillator modes, they are disabled and read `0'.

6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read `0'.

PIC18FXX20

DS39609A-page 36

Advance Information

2003 Microchip Technology Inc.

PORTJ

PIC18F6X20 PIC18F8X20

xxxx xxxx

uuuu uuuu

PORTH

PIC18F6X20 PIC18F8X20

0000 xxxx

0000 uuuu

uuuu uuuu

PORTG

PIC18F6X20 PIC18F8X20

---x xxxx

uuuu uuuu

---u uuuu

PORTF

PIC18F6X20 PIC18F8X20

x000 0000

u000 0000

PORTE

PIC18F6X20 PIC18F8X20

---- -000

---- -uuu

PORTD

PIC18F6X20 PIC18F8X20

xxxx xxxx

uuuu uuuu

PORTC

PIC18F6X20 PIC18F8X20

xxxx xxxx

uuuu uuuu

PORTB

PIC18F6X20 PIC18F8X20

xxxx xxxx

uuuu uuuu

PORTA

(5,6)

PIC18F6X20 PIC18F8X20

-x0x 0000

(5)

-u0u 0000

(5)

-uuu uuuu

(5)

TMR4

PIC18F6X20 PIC18F8X20

0000 0000

uuuu uuuu

PR4

PIC18F6X20 PIC18F8X20

1111 1111

uuuu uuuu

T4CON

PIC18F6X20 PIC18F8X20

-000 0000

-uuu uuuu

CCPR4H

PIC18F6X20 PIC18F8X20

xxxx xxxx

uuuu uuuu

CCPR4L

PIC18F6X20 PIC18F8X20

xxxx xxxx

uuuu uuuu

CCP4CON

PIC18F6X20 PIC18F8X20

0000 0000

uuuu uuuu

CCPR5H

PIC18F6X20 PIC18F8X20

xxxx xxxx

uuuu uuuu

CCPR5L

PIC18F6X20 PIC18F8X20

xxxx xxxx

uuuu uuuu

CCP5CON

PIC18F6X20 PIC18F8X20

0000 0000

uuuu uuuu

SPBRG2

PIC18F6X20 PIC18F8X20

0000 0000

uuuu uuuu

RCREG2

PIC18F6X20 PIC18F8X20

0000 0000

uuuu uuuu

TXREG2

PIC18F6X20 PIC18F8X20

0000 0000

uuuu uuuu

TXSTA2

PIC18F6X20 PIC18F8X20

0000 -010

uuuu -uuu

RCSTA2

PIC18F6X20 PIC18F8X20

0000 000x

uuuu uuuu

TABLE 3-3:

INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

Register

Applicable Devices

Power-on Reset,

Brown-out Reset

MCLR Resets

WDT Reset

RESET

Instruction

Stack Resets

Wake-up via WDT

or Interrupt

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt

vector (0008h or 0018h).

3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.

4: See Table 3-2 for RESET value for specific condition.
5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other

Oscillator modes, they are disabled and read `0'.

6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read `0'.

2003 Microchip Technology Inc.

Advance Information

DS39609A-page 39

PIC18FXX20

4.0

MEMORY ORGANIZATION

There are three memory blocks in PIC18FXX20
devices. They are:
� Program Memory
� Data RAM
� Data EEPROM
Data and program memory use separate busses,
which allows for concurrent access of these blocks.
Additional detailed information for FLASH program
memory and Data EEPROM is provided in Section 5.0
and Section 7.0, respectively.
In addition to on-chip FLASH, the PIC18F8X20 devices
are also capable of accessing external program mem-
ory through an external memory bus. Depending on the
selected Operating mode (discussed in Section 4.1.1),
the controllers may access either internal or external
program memory exclusively, or both internal and
external memory in selected blocks. Additional infor-
mation on the External Memory Interface is provided in
Section 6.0.

4.1

Program Memory Organization

A 21-bit program counter is capable of addressing the
2-Mbyte program memory space. Accessing a location
between the physically implemented memory and the
2-Mbyte address will cause a read of all `0's (a NOP
instruction).
Devices in the PIC18FXX20 family can be divided into
three groups, based on program memory size. The
PIC18FX520 devices (PIC18F6520 and PIC18F8520)
have 32 Kbytes of on-chip FLASH memory, equivalent
to 16,384 single word instructions. The PIC18FX620
devices (PIC18F6620 and PIC18F8620) have
64 Kbytes of on-chip FLASH memory, equivalent to
32,768 single word instructions. Finally, the
PIC18FX720 devices (PIC18F6720 and PIC18F8720)
have 128 Kbytes of on-chip FLASH memory,
equivalent to 65,536 single word instructions.
For all devices, the RESET vector address is at 0000h,
and the interrupt vector addresses are at 0008h and
0018h.
The program memory maps for all of the PIC18FXX20
devices are compared in Figure 4-1.

4.1.1

PIC18F8X20 PROGRAM MEMORY
MODES

PIC18F8X20 devices differ significantly from their
PIC18 predecessors in their utilization of program
memory. In addition to available on-chip FLASH pro-
gram memory, these controllers can also address up to
2 Mbyte of external program memory through external
memory interface. There are four distinct Operating
modes available to the controllers:
� Microprocessor (MP)
� Microprocessor with Boot Block (MPBB)
� Extended Microcontroller (EMC)
� Microcontroller (MC)
The Program Memory mode is determined by setting
the two Least Significant bits of the CONFIG3L config-
uration byte, as shown in Register 4-1. (See also
Section 23.1 for additional details on the device
configuration bits.)
The Program Memory modes operate as follows:
� The Microprocessor Mode permits access only

to external program memory; the contents of the
on-chip FLASH memory are ignored. The 21-bit
program counter permits access to a 2-MByte
linear program memory space.

� The Microprocessor with Boot Block Mode

accesses on-chip FLASH memory from
addresses 000000h to 0007FFh for PIC18F8520
devices, and from 000000h to 0001FFh for
PIC18F8620 and PIC18F8720 devices. Above
this, external program memory is accessed all the
way up to the 2-MByte limit. Program execution
automatically switches between the two
memories, as required.

� The Microcontroller Mode accesses only

on-chip FLASH memory. Attempts to read above
the physical limit of the on-chip FLASH (7FFFh for
the PIC18F8520, 0FFFFh for the PIC18F8620,
1FFFFh for the PIC18F8720) causes a read of all
`0's (a NOP instruction). The Microcontroller mode
is also the only Operating mode available to
PIC18F6X20 devices.

� The Extended Microcontroller Mode allows

access to both internal and external program
memories as a single block. The device can
access its entire on-chip FLASH memory; above
this, the device accesses external program mem-
ory up to the 2-MByte program space limit. As
with Boot Block mode, execution automatically
switches between the two memories, as required.

In all modes, the microcontroller has complete access
to data RAM and EEPROM.
Figure 4-2 compares the memory maps of the different
Program Memory modes. The differences between
on-chip and external memory access limitations are
more fully explained in Table 4-1.

2003 Microchip Technology Inc.

Advance Information

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PIC18FXX20

REGISTER 4-1:

CONFIG3L CONFIGURATION BYTE

FIGURE 4-2:

MEMORY MAPS FOR PIC18F8X20 PROGRAM MEMORY MODES

R/P-1

U-0

R/P-1

WAIT

PM1

PM0

bit 7

bit 0

bit 7

WAIT: External Bus Data Wait Enable bit

= Wait selections unavailable, device will not wait

= Wait programmed by WAIT1 and WAIT0 bits of MEMCOM register (MEMCOM<5:4>)

bit 6-2

Unimplemented: Read as '0'

bit 1-0

PM1:PM0: Processor Data Memory Mode Select bits

= Microcontroller mode

= Microprocessor mode

= Microcontroller with Boot Block mode

= Extended Microcontroller mode

Legend:
R = Readable bit

P = Programmable bit U = Unimplemented bit, read as `0'

- n = Value after erase

`1' = Bit is set

`0' = Bit is cleared

x = Bit is unknown

Microprocessor

Mode (MP)

000000h

1FFFFFh

External
Program
Memory

1FFFFFh

000000h

On-Chip
Program
Memory

Extended

Microcontroller

Mode (EMC)

Microcontroller

Mode (MC)

000000h

External

On-Chip

r
ogr

x
e
c

t
i
o

On-Chip
Program
Memory

1FFFFFh

Reads

Boot+1

1FFFFFh

Boot

Microprocessor
with Boot Block

Mode (MPBB)

000000h

On-Chip
Program

Memory

External
Program
Memory

Memory

FLASH

On-Chip
Program
Memory

(No

access)

`0's

External

On-Chip

Memory

FLASH

On-Chip

FLASH

External

On-Chip

Memory

FLASH

Boundary Values for Microprocessor with Boot Block, Microcontroller and Extended Microcontroller modes

(1)

Note 1:

PIC18F6X20 devices are included here for completeness, to show the boundaries of their boot blocks and program memory spaces.

Device

Boot

Boot+1

Boundary

Boundary+1

Available

Memory Mode(s)

PIC18F6520

0007FFh

000800h

007FFFh

008000h

PIC18F6620

0001FFh

000200h

00FFFFh

010000h

PIC18F6720

0001FFh

000200h

01FFFFh

020000h

PIC18F8520

0007FFh

000800h

007FFFh

008000h

MP, MPBB, MC, EMC

PIC18F8620

0001FFh

000200h

00FFFFh

010000h

MP, MPBB, MC, EMC

PIC18F8720

0001FFh

000200h

01FFFFh

020000h

MP, MPBB, MC, EMC

Boundary

Boundary+1

Boundary

Boundary+1

PIC18FXX20

DS39609A-page 42

Advance Information

2003 Microchip Technology Inc.

4.2

Return Address Stack

The return address stack allows any combination of up
to 31 program calls and interrupts to occur. The PC
(Program Counter) is pushed onto the stack when a
CALL

or RCALL instruction is executed, or an interrupt

is acknowledged. The PC value is pulled off the stack
on a RETURN, RETLW, or a RETFIE instruction.
PCLATU and PCLATH are not affected by any of the
RETURN

or CALL instructions.

The stack operates as a 31-word by 21-bit RAM and a
5-bit stack pointer, with the stack pointer initialized to
00000b after all RESETS. There is no RAM associated
with stack pointer 00000b. This is only a RESET value.
During a CALL type instruction, causing a push onto the
stack, the stack pointer is first incremented and the
RAM location pointed to by the stack pointer is written
with the contents of the PC. During a RETURN type
instruction, causing a pop from the stack, the contents
of the RAM location pointed to by the STKPTR are
transferred to the PC and then the stack pointer is
decremented.
The stack space is not part of either program or data
space. The stack pointer is readable and writable, and
the address on the top of the stack is readable and writ-
able through SFR registers. Data can also be pushed
to, or popped from, the stack using the top-of-stack
SFRs. Status bits indicate if the stack pointer is at, or
beyond the 31 levels provided.

4.2.1

TOP-OF-STACK ACCESS

The top of the stack is readable and writable. Three
register locations, TOSU, TOSH and TOSL hold the
contents of the stack location pointed to by the
STKPTR register. This allows users to implement a
software stack if necessary. After a CALL, RCALL or
interrupt, the software can read the pushed value by
reading the TOSU, TOSH and TOSL registers. These
values can be placed on a user defined software stack.
At return time, the software can replace the TOSU,
TOSH and TOSL and do a return.
The user must disable the global interrupt enable bits
during this time to prevent inadvertent stack
operations.

4.2.2

RETURN STACK POINTER
(STKPTR)

The STKPTR register contains the stack pointer value,
the STKFUL (stack full) status bit, and the STKUNF
(stack underflow) status bits. Register 4-2 shows the
STKPTR register. The value of the stack pointer can be
0 through 31. The stack pointer increments when val-
ues are pushed onto the stack and decrements when
values are popped off the stack. At RESET, the stack
pointer value will be `0'. The user may read and write
the stack pointer value. This feature can be used by a
Real-Time Operating System for return stack
maintenance.
After the PC is pushed onto the stack 31 times (without
popping any values off the stack), the STKFUL bit is
set. The STKFUL bit can only be cleared in software or
by a POR.
The action that takes place when the stack becomes
full, depends on the state of the STVREN (Stack Over-
flow Reset Enable) configuration bit. Refer to
Section 24.0 for a description of the device configura-
tion bits. If STVREN is set (default), the 31st push will
push the (PC + 2) value onto the stack, set the STKFUL
bit, and reset the device. The STKFUL bit will remain
set and the stack pointer will be set to `0'.
If STVREN is cleared, the STKFUL bit will be set on the
31st push and the stack pointer will increment to 31.
Any additional pushes will not overwrite the 31st push,
and STKPTR will remain at 31.
When the stack has been popped enough times to
unload the stack, the next pop will return a value of zero
to the PC and sets the STKUNF bit, while the stack
pointer remains at `0'. The STKUNF bit will remain set
until cleared in software or a POR occurs.

Note:

Returning a value of zero to the PC on an
underflow has the effect of vectoring the
program to the RESET vector, where the
stack conditions can be verified and
appropriate actions can be taken.

2003 Microchip Technology Inc.

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DS39609A-page 43

PIC18FXX20

REGISTER 4-2:

STKPTR REGISTER

FIGURE 4-3:

RETURN ADDRESS STACK AND ASSOCIATED REGISTERS

4.2.3

PUSH AND POP INSTRUCTIONS

Since the Top-of-Stack (TOS) is readable and writable,
the ability to push values onto the stack and pull values
off the stack, without disturbing normal program execu-
tion, is a desirable option. To push the current PC value
onto the stack, a PUSH instruction can be executed.
This will increment the stack pointer and load the cur-
rent PC value onto the stack. TOSU, TOSH and TOSL
can then be modified to place a return address on the
stack.
The ability to pull the TOS value off of the stack and
replace it with the value that was previously pushed
onto the stack, without disturbing normal execution, is
achieved by using the POP instruction. The POP instruc-
tion discards the current TOS by decrementing the
stack pointer. The previous value pushed onto the
stack then becomes the TOS value.

4.2.4

STACK FULL/UNDERFLOW RESETS

These RESETS are enabled by programming the
STVREN configuration bit. When the STVREN bit is
disabled, a full or underflow condition will set the appro-
priate STKFUL or STKUNF bit, but not cause a device
RESET. When the STVREN bit is enabled, a full or
underflow condition will set the appropriate STKFUL or
STKUNF bit and then cause a device RESET. The
STKFUL or STKUNF bits are only cleared by the user
software or a POR Reset.

R/C-0

U-0

R/W-0

STKFUL

(1)

STKUNF

(1)

SP4

SP3

SP2

SP1

SP0

bit 7

bit 0

bit 7

STKFUL: Stack Full Flag bit

= Stack became full or overflowed

= Stack has not become full or overflowed

bit 6

STKUNF: Stack Underflow Flag bit

= Stack underflow occurred

= Stack underflow did not occur

bit 5

Unimplemented: Read as '0'

bit 4-0

SP4:SP0: Stack Pointer Location bits

Note 1: Bit 7 and bit 6 can only be cleared in user software or by a POR.

Legend:
R = Readable bit

W = Writable bit

U = Unimplemented bit, read as `0'

- n = Value at POR

`1' = Bit is set

`0' = Bit is cleared

x = Bit is unknown

00011

0x001A34

11111
11110
11101

00010
00001
00000

00010

Return Address Stack

Top-of-Stack

0x000D58

TOSL

TOSH

TOSU

0x34

0x1A

0x00

STKPTR<4:0>

PIC18FXX20

DS39609A-page 44

Advance Information

2003 Microchip Technology Inc.

4.3

Fast Register Stack

A "fast interrupt return" option is available for interrupts.
A Fast Register Stack is provided for the STATUS,
WREG and BSR registers and is only one in depth. The
stack is not readable or writable and is loaded with the
current value of the corresponding register when the
processor vectors for an interrupt. The values in the
registers are then loaded back into the working regis-
ters, if the FAST RETURN instruction is used to return
from the interrupt.
A low or high priority interrupt source will push values
into the stack registers. If both low and high priority
interrupts are enabled, the stack registers cannot be
used reliably for low priority interrupts. If a high priority
interrupt occurs while servicing a low priority interrupt,
the stack register values stored by the low priority
interrupt will be overwritten.
If high priority interrupts are not disabled during low pri-
ority interrupts, users must save the key registers in
software during a low priority interrupt.
If no interrupts are used, the fast register stack can be
used to restore the STATUS, WREG and BSR registers
at the end of a subroutine call. To use the fast register
stack for a subroutine call, a FAST CALL instruction
must be executed.
Example 4-1 shows a source code example that uses
the fast register stack.

EXAMPLE 4-1:

FAST REGISTER STACK
CODE EXAMPLE

4.4

PCL, PCLATH and PCLATU

The program counter (PC) specifies the address of the
instruction to fetch for execution. The PC is 21-bits
wide. The low byte is called the PCL register; this reg-
ister is readable and writable. The high byte is called
the PCH register. This register contains the PC<15:8>
bits and is not directly readable or writable; updates to
the PCH register may be performed through the
PCLATH register. The upper byte is called PCU. This
register contains the PC<20:16> bits and is not directly
readable or writable; updates to the PCU register may
be performed through the PCLATU register.
The PC addresses bytes in the program memory. To
prevent the PC from becoming misaligned with word
instructions, the LSB of the PCL is fixed to a value of
`0'. The PC increments by 2 to address sequential
instructions in the program memory.
The CALL, RCALL, GOTO and program branch
instructions write to the program counter directly. For
these instructions, the contents of PCLATH and
PCLATU are not transferred to the program counter.
The contents of PCLATH and PCLATU will be trans-
ferred to the program counter by an operation that
writes PCL. Similarly, the upper two bytes of the pro-
gram counter will be transferred to PCLATH and
PCLATU by an operation that reads PCL. This is useful
for computed offsets to the PC (see Section 4.8.1).

4.5

Clocking Scheme/Instruction
Cycle

The clock input (from OSC1) is internally divided by
four to generate four non-overlapping quadrature
clocks, namely Q1, Q2, Q3 and Q4. Internally, the pro-
gram counter (PC) is incremented every Q1, the
instruction is fetched from the program memory and
latched into the instruction register in Q4. The instruc-
tion is decoded and executed during the following Q1
through Q4. The clocks and instruction execution flow
are shown in Figure 4-4.

FIGURE 4-4:

CLOCK/INSTRUCTION CYCLE

CALL SUB1, FAST

;STATUS, WREG, BSR

;SAVED IN FAST REGISTER

;STACK

�
�

SUB1

�
�
�

RETURN FAST

;RESTORE VALUES SAVED

;IN FAST REGISTER STACK

OSC1

Q1
Q2
Q3
Q4

OSC2/CLKO

(RC mode)

PC+2

PC+4

Fetch INST (PC)

Execute INST (PC-2)

Fetch INST (PC+2)

Execute INST (PC)

Fetch INST (PC+4)

Execute INST (PC+2)

Internal

Phase

Clock

2003 Microchip Technology Inc.

Advance Information

DS39609A-page 45

PIC18FXX20

4.6

Instruction Flow/Pipelining

An "Instruction Cycle" consists of four Q cycles (Q1,
Q2, Q3 and Q4). The instruction fetch and execute are
pipelined, such that fetch takes one instruction cycle,
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g., GOTO)
then two cycles are required to complete the instruction
(Example 4-2).

A fetch cycle begins with the program counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the "Instruction Register" (IR) in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3, and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).

EXAMPLE 4-2:

INSTRUCTION PIPELINE FLOW

4.7

Instructions in Program Memory

The program memory is addressed in bytes. Instruc-
tions are stored as two bytes or four bytes in program
memory. The Least Significant Byte of an instruction
word is always stored in a program memory location
with an even address (LSB = 0). Figure 4-5 shows an
example of how instruction words are stored in the pro-
gram memory. To maintain alignment with instruction
boundaries, the PC increments in steps of 2 and the
LSB will always read `0' (see Section 4.4).
The CALL and GOTO instructions have an absolute pro-
gram memory address embedded into the instruction.
Since instructions are always stored on word bound-

aries, the data contained in the instruction is a word
address. The word address is written to PC<20:1>,
which accesses the desired byte address in program
memory. Instruction #2 in Figure 4-5 shows how the
instruction "GOTO 000006h" is encoded in the program
memory. Program branch instructions, which encode a
relative address offset, operate in the same manner.
The offset value stored in a branch instruction repre-
sents the number of single word instructions that the
PC will be offset by. Section 24.0 provides further
details of the instruction set.

FIGURE 4-5:

INSTRUCTIONS IN PROGRAM MEMORY

All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction
is "flushed" from the pipeline, while the new instruction is being fetched and then executed.

1. MOVLW 55h

Fetch 1

Execute 1

2. MOVWF PORTB

Fetch 2

Execute 2

3. BRA SUB_1

Fetch 3

Execute 3

4. BSF PORTA, BIT3 (Forced NOP)

Fetch 4

Flush (NOP)

5. Instruction @ address SUB_1

Fetch SUB_1 Execute SUB_1

Word Address

LSB = 1

LSB = 0

Program Memory
Byte Locations

000000h

000002h

000004h

000006h

Instruction 1:

MOVLW

055h

0Fh

55h

000008h

Instruction 2:

GOTO

000006h

EFh

03h

00000Ah

F0h

00h

00000Ch

Instruction 3:

MOVFF

123h, 456h

C1h

23h

00000Eh

F4h

56h

000010h

000012h

000014h

PIC18FXX20

DS39609A-page 46

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2003 Microchip Technology Inc.

4.7.1

TWO-WORD INSTRUCTIONS

The PIC18FXX20 devices have four two-word instruc-
tions: MOVFF, CALL, GOTO and LFSR. The second
word of these instructions has the 4 MSBs set to `1's
and is a special kind of NOP instruction. The lower 12
bits of the second word contain data to be used by the
instruction. If the first word of the instruction is exe-
cuted, the data in the second word is accessed. If the

second word of the instruction is executed by itself (first
word was skipped), it will execute as a NOP. This action
is necessary when the two-word instruction is preceded
by a conditional instruction that changes the PC. A pro-
gram example that demonstrates this concept is shown
in Example 4-3. Refer to Section 19.0 for further details
of the instruction set.

EXAMPLE 4-3:

TWO-WORD INSTRUCTIONS

4.8

Lookup Tables

Lookup tables are implemented two ways. These are:
� Computed GOTO
� Table Reads

4.8.1

COMPUTED GOTO

A computed GOTO is accomplished by adding an offset
to the program counter (ADDWF PCL).
A lookup table can be formed with an ADDWF PCL
instruction and a group of RETLW 0xnn instructions.
WREG is loaded with an offset into the table before
executing a call to that table. The first instruction of the
called routine is the ADDWF PCL instruction. The next
instruction executed will be one of the RETLW 0xnn
instructions, that returns the value 0xnn to the calling
function.
The offset value (value in WREG) specifies the number
of bytes that the program counter should advance.
In this method, only one data byte may be stored in
each instruction location and room on the return
address stack is required.

4.8.2

TABLE READS/TABLE WRITES

A better method of storing data in program memory
allows 2 bytes of data to be stored in each instruction
location.
Lookup table data may be stored 2 bytes per program
word by using table reads and writes. The table pointer
(TBLPTR) specifies the byte address and the table
latch (TABLAT) contains the data that is read from, or
written to program memory. Data is transferred to/from
program memory, one byte at a time.
A description of the Table Read/Table Write operation
is shown in Section 5.0.

CASE 1:

Object Code

Source Code

0110 0110 0000 0000

TSTFSZ

REG1

; is RAM location 0?

1100 0001 0010 0011

MOVFF

REG1, REG2

; No, execute 2-word instruction

1111 0100 0101 0110

; 2nd operand holds address of REG2

0010 0100 0000 0000

ADDWF

REG3

; continue code

CASE 2:

Object Code

Source Code

0110 0110 0000 0000

TSTFSZ

REG1

; is RAM location 0?

1100 0001 0010 0011

MOVFF

REG1, REG2

; Yes

1111 0100 0101 0110

; 2nd operand becomes NOP

0010 0100 0000 0000

ADDWF

REG3

; continue code

2003 Microchip Technology Inc.

Advance Information

DS39609A-page 47

PIC18FXX20

4.9

Data Memory Organization

The data memory is implemented as static RAM. Each
register in the data memory has a 12-bit address,
allowing up to 4096 bytes of data memory. The data
memory map is in turn divided into 16 banks of 256
bytes each. The lower 4 bits of the Bank Select Regis-
ter (BSR<3:0>) select which bank will be accessed.
The upper 4 bits for the BSR are not implemented.
The data memory space contains both Special Func-
tion Registers (SFR) and General Purpose Registers
(GPR). The SFRs are used for control and status of the
controller and peripheral functions, while GPRs are
used for data storage and scratch pad operations in the
user's application. The SFRs start at the last location of
Bank 15 (0FFFh) and extend downwards. Any remain-
ing space beyond the SFRs in the Bank may be imple-
mented as GPRs. GPRs start at the first location of
Bank 0 and grow upwards. Any read of an
unimplemented location will read as `0's.
PIC18FX520 devices have 2048 bytes of data RAM,
extending from Bank 0 to Bank 7 (000h through 7FFh).
PIC18FX620 and PIC18FX720 devices have
3840 bytes of data RAM, extending from Bank 0 to
Bank 14 (000h through EFFh). The organization of the
data memory space for these devices is shown in
Figure 4-6 and Figure 4-7.
The entire data memory may be accessed directly or
indirectly. Direct addressing may require the use of the
BSR register. Indirect addressing requires the use of a
File Select Register (FSRn) and a corresponding Indi-
rect File Operand (INDFn). Each FSR holds a 12-bit
address value that can be used to access any location
in the Data Memory map without banking.
The instruction set and architecture allow operations
across all banks. This may be accomplished by indirect
addressing, or by the use of the MOVFF instruction. The
MOVFF

instruction is a two-word/two-cycle instruction

that moves a value from one register to another.
To ensure that commonly used registers (SFRs and
select GPRs) can be accessed in a single cycle,
regardless of the current BSR values, an Access Bank
is implemented. A segment of Bank 0 and a segment of
Bank 15 comprise the Access RAM. Section 4.10
provides a detailed description of the Access RAM.

4.9.1

GENERAL PURPOSE REGISTER
FILE

The register file can be accessed either directly or indi-
rectly. Indirect addressing operates using a File Select
Register and corresponding Indirect File Operand. The
operation of indirect addressing is shown in
Section 4.12.
Enhanced MCU devices may have banked memory in
the GPR area. GPRs are not initialized by a Power-on
Reset and are unchanged on all other RESETS.
Data RAM is available for use as general purpose reg-
isters by all instructions. The top section of Bank 15
(F60h to FFFh) contains SFRs. All other banks of data
memory contain GPR registers, starting with Bank 0.

4.9.2

SPECIAL FUNCTION REGISTERS

The Special Function Registers (SFRs) are registers
used by the CPU and Peripheral Modules for control-
ling the desired operation of the device. These regis-
ters are implemented as static RAM. A list of these
registers is given in Table 4-2 and Table 4-3.
The SFRs can be classified into two sets: those asso-
ciated with the "core" function and those related to the
peripheral functions. Those registers related to the
"core" are described in this section, while those related
to the operation of the peripheral features are
described in the section of that peripheral feature. The
SFRs are typically distributed among the peripherals
whose functions they control.
The unused SFR locations are unimplemented and
read as '0's. The addresses for the SFRs are listed in
Table 4-2.

PIC18FXX20

DS39609A-page 50

Advance Information

2003 Microchip Technology Inc.

TABLE 4-2:

SPECIAL FUNCTION REGISTER MAP

Address

Name

Address

Name

Address

Name

Address

Name

FFFh

TOSU

FDFh

INDF2

(3)

FBFh

CCPR1H

F9Fh

IPR1

FFEh

TOSH

FDEh POSTINC2

(3)

FBEh

CCPR1L

F9Eh

PIR1

FFDh

TOSL

FDDh POSTDEC2

(3)

FBDh

CCP1CON

F9Dh

PIE1

FFCh

STKPTR

FDCh

PREINC2

(3)

FBCh

CCPR2H

F9Ch MEMCON

(2)

FFBh

PCLATU

FDBh

PLUSW2

(3)

FBBh

CCPR2L

F9Bh

(1)

FFAh

PCLATH

FDAh

FSR2H

FBAh

CCP2CON

F9Ah

TRISJ

(2)

FF9h

PCL

FD9h

FSR2L

FB9h

CCPR3H

F99h

TRISH

(2)

FF8h

TBLPTRU

FD8h

STATUS

FB8h

CCPR3L

F98h

TRISG

FF7h

TBLPTRH

FD7h

TMR0H

FB7h

CCP3CON

F97h

TRISF

FF6h

TBLPTRL

FD6h

TMR0L

FB6h

(1)

F96h

TRISE

FF5h

TABLAT

FD5h

T0CON

FB5h

CVRCON

F95h

TRISD

FF4h

PRODH

FD4h

(1)

FB4h

CMCON

F94h

TRISC

FF3h

PRODL

FD3h

OSCCON

FB3h

TMR3H

F93h

TRISB

FF2h

INTCON

FD2h

LVDCON

FB2h

TMR3L

F92h

TRISA

FF1h

INTCON2

FD1h

WDTCON

FB1h

T3CON

F91h

LATJ

(2)

FF0h

INTCON3

FD0h

RCON

FB0h

PSPCON

F90h

LATH

(2)

FEFh

INDF0

(3)

FCFh

TMR1H

FAFh

SPBRG1

F8Fh

LATG

FEEh POSTINC0

(3)

FCEh

TMR1L

FAEh

RCREG1

F8Eh

LATF

FEDh POSTDEC0

(3)

FCDh

T1CON

FADh

TXREG1

F8Dh

LATE

FECh

PREINC0

(3)

FCCh

TMR2

FACh

TXSTA1

F8Ch

LATD

FEBh

PLUSW0

(3)

FCBh

PR2

FABh

RCSTA1

F8Bh

LATC

FEAh

FSR0H

FCAh

T2CON

FAAh

EEADRH

F8Ah

LATB

FE9h

FSR0L

FC9h

SSPBUF

FA9h

EEADR

F89h

LATA

FE8h

WREG

FC8h

SSPADD

FA8h

EEDATA

F88h

PORTJ

(2)

FE7h

INDF1

(3)

FC7h

SSPSTAT

FA7h

EECON2

F87h

PORTH

(2)

FE6h POSTINC1

(3)

FC6h

SSPCON1

FA6h

EECON1

F86h

PORTG

FE5h POSTDEC1

(3)

FC5h

SSPCON2

FA5h

IPR3

F85h

PORTF

FE4h

PREINC1

(3)

FC4h

ADRESH

FA4h

PIR3

F84h

PORTE

FE3h

PLUSW1

(3)

FC3h

ADRESL

FA3h

PIE3

F83h

PORTD

FE2h

FSR1H

FC2h

ADCON0

FA2h

IPR2

F82h

PORTC

FE1h

FSR1L

FC1h

ADCON1

FA1h

PIR2

F81h

PORTB

FE0h

BSR

FC0h

ADCON2

FA0h

PIE2

F80h

PORTA

Note 1: Unimplemented registers are read as `0'.

2: This register is not available on PIC18FX520 and PIC18F6X20 devices.
3: This is not a physical register.

2003 Microchip Technology Inc.

Advance Information

DS39609A-page 51

PIC18FXX20

Address

Name

Address

Name

Address

Name

Address

Name

F7Fh

(1)

F5Fh

(1)

F3Fh

(1)

F1Fh

(1)

F7Eh

(1)

F5Eh

(1)

F3Eh

(1)

F1Eh

(1)

F7Dh

(1)

F5Dh

(1)

F3Dh

(1)

F1Dh

(1)

F7Ch

(1)

F5Ch

(1)

F3Ch

(1)

F1Ch

(1)

F7Bh

(1)

F5Bh

(1)

F3Bh

(1)

F1Bh

(1)

F7Ah

(1)

F5Ah

(1)

F3Ah

(1)

F1Ah

(1)

F79h

(1)

F59h

(1)

F39h

(1)

F19h

(1)

F78h

TMR4

F58h

(1)

F38h

(1)

F18h

(1)

F77h

PR4

F57h

(1)

F37h

(1)

F17h

(1)

F76h

T4CON

F56h

(1)

F36h

(1)

F16h

(1)

F75h

CCPR4H

F55h

(1)

F35h

(1)

F15h

(1)

F74h

CCPR4L

F54h

(1)

F34h

(1)

F14h

(1)

F73h

CCP4CON

F53h

(1)

F33h

(1)

F13h

(1)

F72h

CCPR5H

F52h

(1)

F32h

(1)

F12h

(1)

F71h

CCPR5L

F51h

(1)

F31h

(1)

F11h

(1)

F70h

CCP5CON

F50h

(1)

F30h

(1)

F10h

(1)

F6Fh

SPBRG2

F4Fh

(1)

F2Fh

(1)

F0Fh

(1)

F6Eh

RCREG2

F4Eh

(1)

F2Eh

(1)

F0Eh

(1)

F6Dh

TXREG2

F4Dh

(1)

F2Dh

(1)

F0Dh

(1)

F6Ch

TXSTA2

F4Ch

(1)

F2Ch

(1)

F0Ch

(1)

F6Bh

RCSTA2

F4Bh

(1)

F2Bh

(1)

F0Bh

(1)

F6Ah

(1)

F4Ah

(1)

F2Ah

(1)

F0Ah

(1)

F69h

(1)

F49h

(1)

F29h

(1)

F09h

(1)

F68h

(1)

F48h

(1)

F28h

(1)

F08h

(1)

F67h

(1)

F47h

(1)

F27h

(1)

F07h

(1)

F66h

(1)

F46h

(1)

F26h

(1)

F06h

(1)

F65h

(1)

F45h

(1)

F25h

(1)

F05h

(1)

F64h

(1)

F44h

(1)

F24h

(1)

F04h

(1)

F63h

(1)

F43h

(1)

F23h

(1)

F03h

(1)

F62h

(1)

F42h

(1)

F22h

(1)

F02h

(1)

F61h

(1)

F41h

(1)

F21h

(1)

F01h

(1)

F60h

(1)

F40h

(1)

F20h

(1)

F00h

(1)

Note 1: Unimplemented registers are read as `0'.

2: This register is not available on PIC18F6X20 devices.
3: This is not a physical register.

TABLE 4-2:

SPECIAL FUNCTION REGISTER MAP (CONTINUED)

PIC18FXX20

DS39609A-page 52

Advance Information

2003 Microchip Technology Inc.

TABLE 4-3:

REGISTER FILE SUMMARY

File Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR, BOR

Details

page:

TOSU

Top-of-Stack Upper Byte (TOS<20:16>)

---0 0000

32, 42

TOSH

Top-of-Stack High Byte (TOS<15:8>)

0000 0000

32, 42

TOSL

Top-of-Stack Low Byte (TOS<7:0>)

0000 0000

32, 42

STKPTR

STKFUL

STKUNF

Return Stack Pointer

00-0 0000

32, 43

PCLATU

bit21

Holding Register for PC<20:16>

--10 0000

32, 44

PCLATH

Holding Register for PC<15:8>

0000 0000

32, 44

PCL

PC Low Byte (PC<7:0>)

0000 0000

32, 44

TBLPTRU

bit21

(2)

Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)

--00 0000

32, 64

TBLPTRH

Program Memory Table Pointer High Byte (TBLPTR<15:8>)

0000 0000

32, 64

TBLPTRL

Program Memory Table Pointer Low Byte (TBLPTR<7:0>)

0000 0000

32, 64

TABLAT

Program Memory Table Latch

0000 0000

32, 64

PRODH

Product Register High Byte

xxxx xxxx

32, 85

PRODL

Product Register Low Byte

xxxx xxxx

32, 85

INTCON

GIE/GIEH PEIE/GIEL

TMR0IE

INT0IE

RBIE

TMR0IF

INT0IF

RBIF

0000 0000

32, 89

INTCON2

RBPU

INTEDG0

INTEDG1

INTEDG2

INTEDG3

TMR0IP

INT3IP

RBIP

1111 1111

32, 90

INTCON3

INT2IP

INT1IP

INT3IE

INT2IE

INT1IE

INT3IF

INT2IF

INT1IF

1100 0000

32, 91

INDF0

Uses contents of FSR0 to address data memory - value of FSR0 not changed (not a physical register)

n/a

POSTINC0 Uses contents of FSR0 to address data memory - value of FSR0 post-incremented

(not a physical register)

n/a

POSTDEC0 Uses contents of FSR0 to address data memory - value of FSR0 post-decremented

(not a physical register)

n/a

PREINC0

Uses contents of FSR0 to address data memory - value of FSR0 pre-incremented (not a physical register)

n/a

PLUSW0

Uses contents of FSR0 to address data memory - value of FSR0 pre-incremented
(not a physical register) - value of FSR0 offset by value in WREG

n/a

FSR0H

Indirect Data Memory Address Pointer 0 High Byte ---- 0000 32, 57

FSR0L

Indirect Data Memory Address Pointer 0 Low Byte

xxxx xxxx

32, 57

WREG

Working Register

xxxx xxxx

INDF1

Uses contents of FSR1 to address data memory - value of FSR1 not changed (not a physical register)

n/a

POSTINC1 Uses contents of FSR1 to address data memory - value of FSR1 post-incremented

(not a physical register)

n/a

POSTDEC1 Uses contents of FSR1 to address data memory - value of FSR1 post-decremented

(not a physical register)

n/a

PREINC1

Uses contents of FSR1 to address data memory - value of FSR1 pre-incremented
(not a physical register)

n/a

PLUSW1

Uses contents of FSR1 to address data memory - value of FSR1 pre-incremented
(not a physical register) - value of FSR1 offset by value in WREG

n/a

FSR1H

Indirect Data Memory Address Pointer 1 High Byte ---- 0000 33, 57

FSR1L

Indirect Data Memory Address Pointer 1 Low Byte

xxxx xxxx

33, 57

BSR

Bank Select Register

---- 0000

33, 56

INDF2

Uses contents of FSR2 to address data memory - value of FSR2 not changed (not a physical register)

n/a

POSTINC2

Uses contents of FSR2 to address data memory - value of FSR2 post-incremented
(not a physical register)

n/a

POSTDEC2

Uses contents of FSR2 to address data memory - value of FSR2 post-decremented
(not a physical register)

n/a

Legend:

= unknown, u = unchanged, - = unimplemented, q = value depends on condition

Note 1: RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read '0' in all other Oscillator

modes.

2: Bit 21 of the TBLPTRU allows access to the device configuration bits.
3: These registers are unused on PIC18F6X20 devices; always maintain these clear.

2003 Microchip Technology Inc.

Advance Information

DS39609A-page 53

PIC18FXX20

PREINC2

Uses contents of FSR2 to address data memory - value of FSR2 pre-incremented
(not a physical register)

n/a

PLUSW2

Uses contents of FSR2 to address data memory - value of FSR2 pre-incremented
(not a physical register) - value of FSR2 offset by value in WREG

n/a

FSR2H

Indirect Data Memory Address Pointer 2 High Byte ---- 0000 33, 57

FSR2L

Indirect Data Memory Address Pointer 2 Low Byte

xxxx xxxx

33, 57

STATUS

---x xxxx

33, 59

TMR0H

Timer0 Register High Byte

0000 0000

33, 133

TMR0L

Timer0 Register Low Byte

xxxx xxxx

33, 133

T0CON

TMR0ON

T08BIT

T0CS

T0SE

PSA

T0PS2

T0PS1

T0PS0

1111 1111

33, 131

OSCCON

SCS

---- ---0

25, 33

LVDCON

IRVST

LVDEN

LVDL3

LVDL2

LVDL1

LVDL0

--00 0101

33, 235

WDTCON

SWDTE

---- ---0

33, 250

RCON

IPEN

POR

BOR

0--1 11qq

33, 60,

101

TMR1H

Timer1 Register High Byte

xxxx xxxx

33, 135

TMR1L

Timer1 Register Low Byte

xxxx xxxx

33, 135

T1CON

RD16

T1CKPS1

T1CKPS0

T1OSCEN

T1SYNC

TMR1CS

TMR1ON 0-00 0000 33, 135

TMR2

Timer2 Register

0000 0000

33, 141

PR2

Timer2 Period Register

1111 1111

33, 142

T2CON

T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON

T2CKPS1

T2CKPS0 -000 0000 33, 141

SSPBUF

SSP Receive Buffer/Transmit Register

xxxx xxxx

33, 157

SSPADD

SSP Address Register in I

C Slave mode. SSP Baud Rate Reload Register in I

C Master mode.

0000 0000

33, 166

SSPSTAT

SMP

CKE

D/A

R/W

0000 0000

33, 158

SSPCON1

WCOL

SSPOV

SSPEN

CKP

SSPM3

SSPM2

SSPM1

SSPM0

0000 0000

33, 159

SSPCON2

GCEN

ACKSTAT

ACKDT

ACKEN

RCEN

PEN

RSEN

SEN

0000 0000

33, 169

ADRESH

A/D Result Register High Byte

xxxx xxxx

34, 221

ADRESL

A/D Result Register Low Byte

xxxx xxxx

34, 221

ADCON0

CHS3

CHS2

CHS1

CHS0

GO/DONE

ADON

--00 0000

34, 213

ADCON1

VCFG1

VCFG0

PCFG3

PCFG2

PCFG1

PCFG0

--00 0000

34, 214

ADCON2

ADFM

ADCS2

ADCS1

ADCS0

0--- -000

34, 215

CCPR1H

Capture/Compare/PWM Register1 High Byte

xxxx xxxx

153,

155

CCPR1L

Capture/Compare/PWM Register1 Low Byte

xxxx xxxx

153,

155

CCP1CON

DC1B1

DC1B0

CCP1M3

CCP1M2

CCP1M1

CCP1M0 --00 0000 34, 149

CCPR2H

Capture/Compare/PWM Register2 High Byte

xxxx xxxx

34, 153

CCPR2L

Capture/Compare/PWM Register2 Low Byte

xxxx xxxx

34, 153

CCP2CON

DC2B1

DC2B0

CCP2M3

CCP2M2

CCP2M1

CCP2M0 --00 0000 34, 149

CCPR3H

Capture/Compare/PWM Register3 High Byte

xxxx xxxx

34, 153

CCPR3L

Capture/Compare/PWM Register3 Low Byte

xxxx xxxx

34, 153

CCP3CON

DC3B1

DC3B0

CCP3M3

CCP3M2

CCP3M1

CCP3M0 --00 0000 34, 149

CVRCON

CVREN

CVROE

CVRR

CVRSS

CVR3

CVR2

CVR1

CVR0

0000 0000

34, 229

TABLE 4-3:

REGISTER FILE SUMMARY (CONTINUED)

File Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR, BOR

Details

page:

Legend:

= unknown, u = unchanged, - = unimplemented, q = value depends on condition

Note 1: RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read '0' in all other Oscillator

modes.

2: Bit 21 of the TBLPTRU allows access to the device configuration bits.
3: These registers are unused on PIC18F6X20 devices; always maintain these clear.

PIC18FXX20

DS39609A-page 54

Advance Information

2003 Microchip Technology Inc.

CMCON

C2OUT

C1OUT

C2INV

C1INV

CIS

CM2

CM1

CM0

0000 0000

34, 223

TMR3H

Timer3 Register High Byte

xxxx xxxx

34, 143

TMR3L

Timer3 Register Low Byte

xxxx xxxx

34, 143

T3CON

RD16

T3CCP2

T3CKPS1

T3CKPS0

T3CCP1

T3SYNC

TMR3CS

TMR3ON 0000 0000 34, 143

PSPCON

IBF

OBF

IBOV

PSPMODE

0000 ----

34, 129

SPBRG1

USART1 Baud Rate Generator

0000 0000

34, 205

RCREG1

USART1 Receive Register

0000 0000

34, 207

TXREG1

USART1 Transmit Register

0000 0000

34, 205

TXSTA1

CSRC

TX9

TXEN

SYNC

BRGH

TRMT

TX9D

0000 -010

34, 198

RCSTA1

SPEN

RX9

SREN

CREN

ADDEN

FERR

OERR

RX9D

0000 000x

34, 199

EEADRH

EE Adr Register High

---- --00

34, 83

EEADR

Data EEPROM Address Register

0000 0000

34, 83

EEDATA

Data EEPROM Data Register

0000 0000

34, 83

EECON2

Data EEPROM Control Register 2 (not a physical register)

---- ----

34, 83

EECON1

EEPGD

CFGS

FREE

WRERR

WREN

00-0 x000

34, 80

IPR3

RC2IP

TX2IP

TMR4IP

CCP5IP

CCP4IP

CCP3IP

--11 1111

35, 100

PIR3

RC2IF

TX2IF

TMR4IF

CCP5IF

CCP4IF

CCP3IF

--00 0000

35, 94

PIE3

RC2IE

TX2IE

TMR4IE

CCP5IE

CCP4IE

CCP3IE

--00 0000

35, 97

IPR2

CMIP

EEIP

BCLIP

LVDIP

TMR3IP

CCP2IP

-1-1 1111

35, 99

PIR2

CMIF

EEIF

BCLIF

LVDIF

TMR3IF

CCP2IF

-0-0 0000

35, 93

PIE2

CMIE

EEIE

BCLIE

LVDIE

TMR3IE

CCP2IE

-0-0 0000

35, 96

IPR1

PSPIP

ADIP

RCIP

TXIP

SSPIP

CCP1IP

TMR2IP

TMR1IP

0111 1111

35, 98

PIR1

PSPIF

ADIF

RCIF

TXIF

SSPIF

CCP1IF

TMR2IF

TMR1IF

0000 0000

35, 92

PIE1

PSPIE

ADIE

RCIE

TXIE

SSPIE

CCP1IE

TMR2IE

TMR1IE

0000 0000

35, 95

MEMCON

(3)

EBDIS

WAIT1

WAIT0

WM1

WM0

0-00 --00

35, 71

TRISJ

(3)

Data Direction Control Register for PORTJ

1111 1111

35, 127

TRISH

(3)

Data Direction Control Register for PORTH

1111 1111

35, 124

TRISG

Data Direction Control Register for PORTG

---1 1111

35, 121

TRISF

Data Direction Control Register for PORTF

1111 1111

35, 119

TRISE

Data Direction Control Register for PORTE

1111 1111

35, 116

TRISD

Data Direction Control Register for PORTD

1111 1111

35, 113

TRISC

Data Direction Control Register for PORTC

1111 1111

35, 109

TRISB

Data Direction Control Register for PORTB

1111 1111

35, 106

TRISA

TRISA6

(1)

Data Direction Control Register for PORTA

-111 1111

35, 103

LATJ

(3)

Read PORTJ Data Latch, Write PORTJ Data Latch

xxxx xxxx

35, 127

LATH

(3)

Read PORTH Data Latch, Write PORTH Data Latch

xxxx xxxx

35, 124

LATG

Read PORTG Data Latch, Write PORTG Data Latch

---x xxxx

35, 121

LATF

Read PORTF Data Latch, Write PORTF Data Latch

xxxx xxxx

35, 119

LATE

Read PORTE Data Latch, Write PORTE Data Latch

xxxx xxxx

35, 116

LATD

Read PORTD Data Latch, Write PORTD Data Latch

xxxx xxxx

35, 111

LATC

Read PORTC Data Latch, Write PORTC Data Latch

xxxx xxxx

35, 109

LATB

Read PORTB Data Latch, Write PORTB Data Latch

xxxx xxxx

35, 106

TABLE 4-3:

REGISTER FILE SUMMARY (CONTINUED)

File Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR, BOR

Details

page:

Legend:

= unknown, u = unchanged, - = unimplemented, q = value depends on condition

Note 1: RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read '0' in all other Oscillator

modes.

2: Bit 21 of the TBLPTRU allows access to the device configuration bits.
3: These registers are unused on PIC18F6X20 devices; always maintain these clear.

2003 Microchip Technology Inc.

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PIC18FXX20

LATA

LATA6

(1)

Read PORTA Data Latch, Write PORTA Data Latch

(1)

-xxx xxxx

35, 103

PORTJ

(3)

Read PORTJ pins, Write PORTJ Data Latch

xxxx xxxx

36, 127

PORTH

(3)

Read PORTH pins, Write PORTH Data Latch

xxxx xxxx

36, 124

PORTG

Read PORTG pins, Write PORTG Data Latch

---x xxxx

36, 121

PORTF

Read PORTF pins, Write PORTF Data Latch

xxxx xxxx

36, 119

PORTE

Read PORTE pins, Write PORTE Data Latch

xxxx xxxx

36, 114

PORTD

Read PORTD pins, Write PORTD Data Latch

xxxx xxxx

36, 111

PORTC

Read PORTC pins, Write PORTC Data Latch

xxxx xxxx

36, 109

PORTB

Read PORTB pins, Write PORTB Data Latch

xxxx xxxx

36, 106

PORTA

RA6

(1)

Read PORTA pins, Write PORTA Data Latch

(1)

-x0x 0000

36, 103

TMR4

Timer4 Register

0000 0000

36, 148

PR4

Timer4 Period Register

1111 1111

36, 148

T4CON

T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON

T4CKPS1

T4CKPS0 -000 0000 36, 147

CCPR4H

Capture/Compare/PWM Register 4 High Byte

xxxx xxxx

36, 153

CCPR4L

Capture/Compare/PWM Register 4 Low Byte

xxxx xxxx

36, 153

CCP4CON

DC4B1

DC4B0

CCP4M3

CCP4M2

CCP4M1

CCP4M0 0000 0000 36, 149

CCPR5H

Capture/Compare/PWM Register 5 High Byte

xxxx xxxx

36, 153

CCPR5L

Capture/Compare/PWM Register 5 Low Byte

xxxx xxxx

36, 153

CCP5CON

DC5B1

DC5B0

CCP5M3

CCP5M2

CCP5M1

CCP5M0 0000 0000 36, 149

SPBRG2

USART2 Baud Rate Generator

0000 0000

36, 205

RCREG2

USART2 Receive Register

0000 0000

36, 205

TXREG2

USART2 Transmit Register

0000 0000

36, 205

TXSTA2

CSRC

TX9

TXEN

SYNC

BRGH

TRMT

TX9D

0000 -010

36, 198

RCSTA2

SPEN

RX9

SREN

CREN

ADDEN

FERR

OERR

RX9D

0000 000x

36, 199

TABLE 4-3:

REGISTER FILE SUMMARY (CONTINUED)

File Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR, BOR

Details

page:

Legend:

= unknown, u = unchanged, - = unimplemented, q = value depends on condition

Note 1: RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read '0' in all other Oscillator

modes.

2: Bit 21 of the TBLPTRU allows access to the device configuration bits.
3: These registers are unused on PIC18F6X20 devices; always maintain these clear.

PIC18FXX20

DS39609A-page 56

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4.10

Access Bank

The Access Bank is an architectural enhancement,
which is very useful for C compiler code optimization.
The techniques used by the C compiler may also be
useful for programs written in assembly.
This data memory region can be used for:
� Intermediate computational values
� Local variables of subroutines
� Faster context saving/switching of variables
� Common variables
� Faster evaluation/control of SFRs (no banking)
The Access Bank is comprised of the upper 160 bytes
in Bank 15 (SFRs) and the lower 96 bytes in Bank 0.
These two sections will be referred to as Access RAM
High and Access RAM Low, respectively. Figure 4-7
indicates the Access RAM areas.
A bit in the instruction word specifies if the operation is
to occur in the bank specified by the BSR register or in
the Access Bank. This bit is denoted by the `a' bit (for
access bit).
When forced in the Access Bank (a = 0), the last
address in Access RAM Low is followed by the first
address in Access RAM High. Access RAM High maps
the Special Function registers, so that these registers
can be accessed without any software overhead. This is
useful for testing status flags and modifying control bits.

4.11

Bank Select Register (BSR)

The need for a large general purpose memory space
dictates a RAM banking scheme. The data memory is
partitioned into sixteen banks. When using direct
addressing, the BSR should be configured for the
desired bank.
BSR<3:0> holds the upper 4 bits of the 12-bit RAM
address. The BSR<7:4> bits will always read `0's, and
writes will have no effect.
A MOVLB instruction has been provided in the
instruction set to assist in selecting banks.
If the currently selected bank is not implemented, any
read will return all '0's and all writes are ignored. The
STATUS register bits will be set/cleared as appropriate
for the instruction performed.
Each Bank extends up to FFh (256 bytes). All data
memory is implemented as static RAM.
A MOVFF instruction ignores the BSR, since the 12-bit
addresses are embedded into the instruction word.
Section 4.12 provides a description of indirect address-
ing, which allows linear addressing of the entire RAM
space.

FIGURE 4-8:

DIRECT ADDRESSING

Note 1: For register file map detail, see Table 4-2.

2: The access bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the

registers of the Access Bank.

3: The MOVFF instruction embeds the entire 12-bit address in the instruction.

Data

Memory

(1)

Direct Addressing

Bank Select

(2)

Location Select

(3)

BSR<3:0>

From Opcode

(3)

00h

01h

0Eh

0Fh

Bank 0

Bank 1

Bank 14 Bank 15

1FFh

100h

0FFh

000h

EFFh

E00h

FFFh

F00h

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PIC18FXX20

4.12

Indirect Addressing, INDF and
FSR Registers

Indirect addressing is a mode of addressing data mem-
ory, where the data memory address in the instruction
is not fixed. An FSR register is used as a pointer to the
data memory location that is to be read or written. Since
this pointer is in RAM, the contents can be modified by
the program. This can be useful for data tables in the
data memory and for software stacks. Figure 4-9
shows the operation of indirect addressing. This shows
the moving of the value to the data memory address,
specified by the value of the FSR register.
Indirect addressing is possible by using one of the
INDF registers. Any instruction using the INDF register
actually accesses the register pointed to by the File
Select Register, FSR. Reading the INDF register itself,
indirectly (FSR = 0), will read 00h. Writing to the INDF
register indirectly, results in a no operation. The FSR
register contains a 12-bit address, which is shown in
Figure 4-10.
The INDFn register is not a physical register. Address-
ing INDFn actually addresses the register whose
address is contained in the FSRn register (FSRn is a
pointer). This is indirect addressing.
Example 4-4 shows a simple use of indirect addressing
to clear the RAM in Bank 1 (locations 100h-1FFh) in a
minimum number of instructions.

EXAMPLE 4-4:

HOW TO CLEAR RAM
(BANK 1) USING
INDIRECT ADDRESSING

There are three indirect addressing registers. To
address the entire data memory space (4096 bytes),
these registers are 12-bits wide. To store the 12 bits of
addressing information, two 8-bit registers are
required. These indirect addressing registers are:
1.

FSR0: composed of FSR0H:FSR0L

FSR1: composed of FSR1H:FSR1L

FSR2: composed of FSR2H:FSR2L

In addition, there are registers INDF0, INDF1 and
INDF2, which are not physically implemented. Reading
or writing to these registers activates indirect address-
ing, with the value in the corresponding FSR register
being the address of the data. If an instruction writes a
value to INDF0, the value will be written to the address
pointed to by FSR0H:FSR0L. A read from INDF1 reads

the data from the address pointed to by
FSR1H:FSR1L. INDFn can be used in code anywhere
an operand can be used.
If INDF0, INDF1, or INDF2 are read indirectly via an
FSR, all '0's are read (zero bit is set). Similarly, if
INDF0, INDF1, or INDF2 are written to indirectly, the
operation will be equivalent to a NOP instruction and the
STATUS bits are not affected.

4.12.1

INDIRECT ADDRESSING
OPERATION

Each FSR register has an INDF register associated
with it, plus four additional register addresses. Perform-
ing an operation on one of these five registers deter-
mines how the FSR will be modified during indirect
addressing.
When data access is done to one of the five INDFn
locations, the address selected will configure the FSRn
register to:
� Do nothing to FSRn after an indirect access (no

change) - INDFn.

� Auto-decrement FSRn after an indirect access

(post-decrement) - POSTDECn.

� Auto-increment FSRn after an indirect access

(post-increment) - POSTINCn.

� Auto-increment FSRn before an indirect access

(pre-increment) - PREINCn.

� Use the value in the WREG register as an offset

to FSRn. Do not modify the value of the WREG or
the FSRn register after an indirect access (no
change) - PLUSWn.

When using the auto-increment or auto-decrement fea-
tures, the effect on the FSR is not reflected in the
STATUS register. For example, if the indirect address
causes the FSR to equal '0', the Z bit will not be set.
Incrementing or decrementing an FSR affects all 12
bits. That is, when FSRnL overflows from an increment,
FSRnH will be incremented automatically.
Adding these features allows the FSRn to be used as a
stack pointer, in addition to its uses for table operations
in data memory.
Each FSR has an address associated with it that per-
forms an indexed indirect access. When a data access
to this INDFn location (PLUSWn) occurs, the FSRn is
configured to add the signed value in the WREG regis-
ter and the value in FSR to form the address before an
indirect access. The FSR value is not changed.
If an FSR register contains a value that points to one of
the INDFn, an indirect read will read 00h (zero bit is
set), while an indirect write will be equivalent to a NOP
(STATUS bits are not affected).
If an indirect addressing operation is done where the
target address is an FSRnH or FSRnL register, the
write operation will dominate over the pre- or
post-increment/decrement functions.

LFSR FSR0 ,0x100

;

CLRF POSTINC0

; Clear INDF

; register and

; inc pointer

BTFSS FSR0H, 1 ; All done with

; Bank 1?

GOTO NEXT ; NO, clear next

CONTINUE

; YES, continue

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DS39609A-page 59

PIC18FXX20

4.13

STATUS Register

The STATUS register, shown in Register 4-3, contains
the arithmetic status of the ALU. The STATUS register
can be the destination for any instruction, as with any
other register. If the STATUS register is the destination
for an instruction that affects the Z, DC, C, OV, or N bits,
then the write to these five bits is disabled. These bits are
set or cleared according to the device logic. Therefore,
the result of an instruction with the STATUS register as
destination may be different than intended.

For example, CLRF STATUS will clear the upper three
bits and set the Z bit. This leaves the STATUS register
as 000u u1uu (where u = unchanged).
It is recommended, therefore, that only BCF, BSF,
SWAPF, MOVFF

and MOVWF instructions are used to

alter the STATUS register, because these instructions
do not affect the Z, C, DC, OV, or N bits from the
STATUS register. For other instructions not affecting
any status bits, see Table 24-2.

REGISTER 4-3:

STATUS REGISTER

Note:

The C and DC bits operate as a borrow and
digit borrow bit respectively, in subtraction.

U-0

R/W-x

bit 7

bit 0

bit 7-5

Unimplemented: Read as '0'

bit 4

N: Negative bit
This bit is used for signed arithmetic (2's complement). It indicates whether the result was
negative (ALU MSB = 1).

= Result was negative

= Result was positive

bit 3

OV: Overflow bit
This bit is used for signed arithmetic (2's complement). It indicates an overflow of the
7-bit magnitude, which causes the sign bit (bit 7) to change state.

= Overflow occurred for signed arithmetic (in this arithmetic operation)

= No overflow occurred

bit 2

Z: Zero bit

= The result of an arithmetic or logic operation is zero

= The result of an arithmetic or logic operation is not zero

bit 1

DC: Digit carry/borrow bit
For ADDWF, ADDLW, SUBLW, and SUBWF instructions

= A carry-out from the 4th low order bit of the result occurred

= No carry-out from the 4th low order bit of the result

Note:

For borrow, the polarity is reversed. A subtraction is executed by adding the two's
complement of the second operand. For rotate (RRF, RLF) instructions, this bit is
loaded with either bit 4 or bit 3 of the source register.

bit 0

C: Carry/borrow bit
For ADDWF, ADDLW, SUBLW, and SUBWF instructions

= A carry-out from the Most Significant bit of the result occurred

= No carry-out from the Most Significant bit of the result occurred

Note:

Legend:
R = Readable bit

W = Writable bit

U = Unimplemented bit, read as `0'

- n = Value at POR

`1' = Bit is set

`0' = Bit is cleared

x = Bit is unknown

PIC18FXX20

DS39609A-page 60

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4.14

RCON Register

The RESET Control (RCON) register contains flag bits
that allow differentiation between the sources of a
device RESET. These flags include the TO, PD, POR,
BOR and RI bits. This register is readable and writable.

REGISTER 4-4:

RCON REGISTER

Note 1: If the BOREN configuration bit is set

(Brown-out Reset enabled), the BOR bit
is `1' on a Power-on Reset. After a
Brown-out Reset has occurred, the BOR
bit will be cleared, and must be set by
firmware to indicate the occurrence of the
next Brown-out Reset.

2: It is recommended that the POR bit be set

after a Power-on Reset has been
detected, so that subsequent Power-on
Resets may be detected.

R/W-0

U-0

R/W-1

R/W-0

IPEN

POR

BOR

bit 7

bit 0

bit 7

IPEN: Interrupt Priority Enable bit

= Enable priority levels on interrupts

= Disable priority levels on interrupts (PIC16CXXX Compatibility mode)

bit 6-5

Unimplemented: Read as '0'

bit 4

RI: RESET Instruction Flag bit

= The RESET instruction was not executed

= The RESET instruction was executed causing a device RESET

(must be set in software after a Brown-out Reset occurs)

bit 3

TO: Watchdog Time-out Flag bit

= After power-up, CLRWDT instruction, or SLEEP instruction

= A WDT time-out occurred

bit 2

PD: Power-down Detection Flag bit

= After power-up or by the CLRWDT instruction

= By execution of the SLEEP instruction

bit 1

POR: Power-on Reset Status bit

= A Power-on Reset has not occurred

= A Power-on Reset occurred

(must be set in software after a Power-on Reset occurs)

bit 0

BOR: Brown-out Reset Status bit

= A Brown-out Reset has not occurred

= A Brown-out Reset occurred

(must be set in software after a Brown-out Reset occurs)

Legend:
R = Readable bit

W = Writable bit

U = Unimplemented bit, read as `0'

- n = Value at POR

`1' = Bit is set

`0' = Bit is cleared

x = Bit is unknown

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PIC18FXX20

5.0

FLASH PROGRAM MEMORY

The FLASH Program Memory is readable, writable,
and erasable, during normal operation over the entire
V

range.

A read from program memory is executed on one byte
at a time. A write to program memory is executed on
blocks of 8 bytes at a time. Program memory is erased
in blocks of 64 bytes at a time. A bulk erase operation
may not be issued from user code.
Writing or erasing program memory will cease instruc-
tion fetches until the operation is complete. The pro-
gram memory cannot be accessed during the write or
erase, therefore, code cannot execute. An internal pro-
gramming timer terminates program memory writes
and erases.
A value written to program memory does not need to be
a valid instruction. Executing a program memory loca-
tion that forms an invalid instruction results in a NOP.

5.1

Table Reads and Table Writes

In order to read and write program memory, there are
two operations that allow the processor to move bytes
between the program memory space and the data
RAM:
� Table Read (TBLRD)
� Table Write (TBLWT)

The program memory space is 16-bits wide, while the
data RAM space is 8-bits wide. Table Reads and Table
Writes move data between these two memory spaces
through an 8-bit register (TABLAT).
Table Read operations retrieve data from program
memory and place it into the data RAM space.
Figure 5-1 shows the operation of a Table Read with
program memory and data RAM.
Table Write operations store data from the data mem-
ory space into holding registers in program memory.
The procedure to write the contents of the holding reg-
isters into program memory is detailed in Section 5.5,
'"Writing to FLASH Program Memory". Figure 5-2
shows the operation of a Table Write with program
memory and data RAM.
Table operations work with byte entities. A table block
containing data, rather than program instructions, is not
required to be word aligned. Therefore, a table block
can start and end at any byte address. If a Table Write
is being used to write executable code into program
memory, program instructions will need to be word
aligned.

FIGURE 5-1:

TABLE READ OPERATION

Table Pointer

(1)

Table Latch (8-bit)

Program Memory

TBLPTRH

TBLPTRL

TABLAT

TBLPTRU

Instruction: TBLRD*

Note 1: Table Pointer points to a byte in program memory.

Program Memory
(TBLPTR)

PIC18FXX20

DS39609A-page 62

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2003 Microchip Technology Inc.

FIGURE 5-2:

TABLE WRITE OPERATION

5.2

Control Registers

Several control registers are used in conjunction with
the TBLRD and TBLWT instructions. These include the:
� EECON1 register
� EECON2 register
� TABLAT register
� TBLPTR registers

5.2.1

EECON1 AND EECON2 REGISTERS

EECON1 is the control register for memory accesses.
EECON2 is not a physical register. Reading EECON2
will read all '0's. The EECON2 register is used
exclusively in the memory write and erase sequences.
Control bit EEPGD determines if the access will be a
program or data EEPROM memory access. When
clear, any subsequent operations will operate on the
data EEPROM memory. When set, any subsequent
operations will operate on the program memory.
Control bit CFGS determines if the access will be to the
configuration/calibration registers, or to program
memory/data EEPROM memory. When set, subse-
quent operations will operate on configuration regis-
ters, regardless of EEPGD (see "Special Features of
the CPU", Section 23.0). When clear, memory
selection access is determined by EEPGD.

The FREE bit, when set, will allow a program memory
erase operation. When the FREE bit is set, the erase
operation is initiated on the next WR command. When
FREE is clear, only writes are enabled.
The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is clear. The WRERR bit is
set when a write operation is interrupted by a MCLR
Reset, or a WDT Time-out Reset during normal opera-
tion. In these situations, the user can check the
WRERR bit and rewrite the location. It is necessary to
reload the data and address registers (EEDATA and
EEADR), due to RESET values of zero.
The WR control bit, WR, initiates write operations. The
bit cannot be cleared, only set, in software; it is cleared
in hardware at the completion of the write operation.
The inability to clear the WR bit in software prevents the
accidental or premature termination of a write
operation.

Table Pointer

(1)

Table Latch (8-bit)

TBLPTRH

TBLPTRL

TABLAT

Program Memory
(TBLPTR)

TBLPTRU

Instruction: TBLWT*

Note 1: Table Pointer actually points to one of eight holding registers, the address of which is determined by

TBLPTRL<2:0>. The process for physically writing data to the Program Memory Array is discussed in
Section 5.5.

Holding Registers

Program Memory

Note:

Interrupt flag bit, EEIF in the PIR2 register,
is set when the write is complete. It must
be cleared in software.

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PIC18FXX20

REGISTER 5-1:

EECON1 REGISTER (ADDRESS FA6h)

R/W-x

U-0

R/W-0

R/W-x

R/W-0

R/S-0

EEPGD

CFGS

FREE

WRERR

WREN

bit 7

bit 0

bit 7

EEPGD: FLASH Program or Data EEPROM Memory Select bit

= Access FLASH Program memory

= Access Data EEPROM memory

bit 6

CFGS: FLASH Program/Data EEPROM or Configuration Select bit

= Access Configuration registers

= Access FLASH Program or Data EEPROM memory

bit 5

Unimplemented: Read as '0'

bit 4

FREE: FLASH Row Erase Enable bit

= Erase the program memory row addressed by TBLPTR on the next WR command

(cleared by completion of erase operation)

= Perform write only

bit 3

WRERR: FLASH Program/Data EEPROM Error Flag bit

= A write operation is prematurely terminated

(any RESET during self-timed programming in normal operation)

= The write operation completed

Note: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows

tracing of the error condition.

bit 2

WREN: FLASH Program/Data EEPROM Write Enable bit

= Allows write cycles to FLASH Program/Data EEPROM

= Inhibits write cycles to FLASH Program/Data EEPROM

bit 1

WR: Write Control bit

= Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle.

(The operation is self-timed and the bit is cleared by hardware once write is complete. The
WR bit can only be set (not cleared) in software.)

= Write cycle to the EEPROM is complete

bit 0

RD: Read Control bit

= Initiates an EEPROM read

(Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared)
in software. RD bit cannot be set when EEPGD = 1.)

= Does not initiate an EEPROM read

Legend:
R = Readable bit

W = Writable bit

U = Unimplemented bit, read as `0'

- n = Value at POR

`1' = Bit is set

`0' = Bit is cleared

x = Bit is unknown

PIC18FXX20

DS39609A-page 64

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2003 Microchip Technology Inc.

5.2.2

TABLAT - TABLE LATCH REGISTER

The Table Latch (TABLAT) is an 8-bit register mapped
into the SFR space. The Table Latch is used to hold
8-bit data during data transfers between program
memory and data RAM.

5.2.3

TBLPTR - TABLE POINTER
REGISTER

The Table Pointer (TBLPTR) addresses a byte within
the program memory. The TBLPTR is comprised of
three SFR registers: Table Pointer Upper Byte, Table
Pointer High Byte and Table Pointer Low Byte
(TBLPTRU:TBLPTRH:TBLPTRL). These three regis-
ters join to form a 22-bit wide pointer. The low order 21
bits allow the device to address up to 2 Mbytes of pro-
gram memory space. The 22nd bit allows access to the
Device ID, the User ID and the Configuration bits.
The table pointer, TBLPTR, is used by the TBLRD and
TBLWT

instructions. These instructions can update the

TBLPTR in one of four ways, based on the table oper-
ation. These operations are shown in Table 5-1. These
operations on the TBLPTR only affect the low order
21 bits.

5.2.4

TABLE POINTER BOUNDARIES

TBLPTR is used in reads, writes, and erases of the
FLASH program memory.
When a TBLRD is executed, all 22 bits of the Table
Pointer determine which byte is read from program
memory into TABLAT.
When a TBLWT is executed, the three LSbs of the Table
Pointer (TBLPTR<2:0>) determine which of the eight
program memory holding registers is written to. When
the timed write to program memory (long write) begins,
the 19 MSbs of the Table Pointer, TBLPTR
(TBLPTR<21:3>), will determine which program mem-
ory block of 8 bytes is written to. For more detail, see
Section 5.5 ("Writing to FLASH Program Memory").
When an erase of program memory is executed, the 16
MSbs of the Table Pointer (TBLPTR<21:6>) point to the
64-byte block that will be erased. The Least Significant
bits (TBLPTR<5:0>) are ignored.
Figure 5-3 describes the relevant boundaries of
TBLPTR based on FLASH program memory
operations.

TABLE 5-1:

TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS

FIGURE 5-3:

TABLE POINTER BOUNDARIES BASED ON OPERATION

Example

Operation on Table Pointer

TBLRD*

TBLWT*

TBLPTR is not modified

TBLRD*+

TBLWT*+

TBLPTR is incremented after the read/write

TBLRD*-

TBLWT*-

TBLPTR is decremented after the read/write

TBLRD+*

TBLWT+*

TBLPTR is incremented before the read/write

ERASE - TBLPTR<20:6>

WRITE - TBLPTR<21:3>

READ - TBLPTR<21:0>

TBLPTRL

TBLPTRH

TBLPTRU

PIC18FXX20

DS39609A-page 66

Advance Information

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5.4

Erasing FLASH Program Memory

The minimum erase block is 32 words or 64 bytes. Only
through the use of an external programmer, or through
ICSP control, can larger blocks of program memory be
bulk erased. Word erase in the FLASH array is not
supported.
When initiating an erase sequence from the micro-
controller itself, a block of 64 bytes of program memory
is erased. The Most Significant 16 bits of the
TBLPTR<21:6> point to the block being erased.
TBLPTR<5:0> are ignored.
The EECON1 register commands the erase operation.
The EEPGD bit must be set to point to the FLASH pro-
gram memory. The WREN bit must be set to enable
write operations. The FREE bit is set to select an erase
operation.
For protection, the write initiate sequence for EECON2
must be used.
A long write is necessary for erasing the internal
FLASH. Instruction execution is halted while in a long
write cycle. The long write will be terminated by the
internal programming timer.

5.4.1

FLASH PROGRAM MEMORY
ERASE SEQUENCE

The sequence of events for erasing a block of internal
program memory location is:
1.

Load table pointer with address of row being
erased.

Set the EECON1 register for the erase operation:
� set EEPGD bit to point to program memory;
� clear the CFGS bit to access program memory;
� set WREN bit to enable writes;
� set FREE bit to enable the erase.

Disable interrupts.

Write 55h to EECON2.

Write AAh to EECON2.

Set the WR bit. This will begin the row erase
cycle.

The CPU will stall for duration of the erase
(about 2 ms using internal timer).

Execute a NOP.

Re-enable interrupts.

EXAMPLE 5-2:

ERASING A FLASH PROGRAM MEMORY ROW

MOVLW

CODE_ADDR_UPPER

; load TBLPTR with the base

MOVWF

TBLPTRU

; address of the memory block

MOVLW

CODE_ADDR_HIGH

MOVWF

TBLPTRH

MOVLW

CODE_ADDR_LOW

MOVWF

TBLPTRL

ERASE_ROW

BSF

EECON1,EEPGD

; point to FLASH program memory

BCF

EECON1,CFGS

; access FLASH program memory

BSF

EECON1,WREN

; enable write to memory

BSF

EECON1,FREE

; enable Row Erase operation

BCF

INTCON,GIE

; disable interrupts

Required

MOVLW

55h

Sequence

MOVWF

EECON2

; write 55H

MOVLW

AAh

MOVWF

EECON2

; write AAH

BSF

EECON1,WR

; start erase (CPU stall)

NOP

BSF

INTCON,GIE

; re-enable interrupts

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PIC18FXX20

EXAMPLE 5-3:

WRITING TO FLASH PROGRAM MEMORY

MOVLW

D'64

; number of bytes in erase block

MOVWF

COUNTER

MOVLW

BUFFER_ADDR_HIGH

; point to buffer

MOVWF

FSR0H

MOVLW

BUFFER_ADDR_LOW

MOVWF

FSR0L

MOVLW

CODE_ADDR_UPPER

; Load TBLPTR with the base

MOVWF

TBLPTRU

; address of the memory block

MOVLW

CODE_ADDR_HIGH

MOVWF

TBLPTRH

MOVLW

CODE_ADDR_LOW

MOVWF

TBLPTRL

READ_BLOCK

TBLRD*+

; read into TABLAT, and inc

MOVF

TABLAT, W

; get data

MOVWF

POSTINC0

; store data

DECFSZ

COUNTER ;

done?

BRA

READ_BLOCK

; repeat

MODIFY_WORD

MOVLW

DATA_ADDR_HIGH

; point to buffer

MOVWF

FSR0H

MOVLW

DATA_ADDR_LOW

MOVWF

FSR0L

MOVLW

NEW_DATA_LOW

; update buffer word

MOVWF

POSTINC0

MOVLW

NEW_DATA_HIGH

MOVWF

INDF0

ERASE_BLOCK

MOVLW

CODE_ADDR_UPPER

; load TBLPTR with the base

MOVWF

TBLPTRU

; address of the memory block

MOVLW

CODE_ADDR_HIGH

MOVWF

TBLPTRH

MOVLW

CODE_ADDR_LOW

MOVWF

TBLPTRL

BSF

EECON1,EEPGD

; point to FLASH program memory

BCF

EECON1,CFGS

; access FLASH program memory

BSF

EECON1,WREN

; enable write to memory

BSF

EECON1,FREE

; enable Row Erase operation

BCF

INTCON,GIE

; disable interrupts

MOVLW

55h

Required

MOVWF

EECON2

; write 55H

Sequence

MOVLW

AAh

MOVWF

EECON2

; write AAH

BSF

EECON1,WR

; start erase (CPU stall)

NOP

BSF

INTCON,GIE

; re-enable interrupts

TBLRD*-

; dummy read decrement

WRITE_BUFFER_BACK

MOVLW

; number of write buffer groups of 8 bytes

MOVWF

COUNTER_HI

MOVLW

BUFFER_ADDR_HIGH

; point to buffer

MOVWF

FSR0H

MOVLW

BUFFER_ADDR_LOW

MOVWF

FSR0L

PROGRAM_LOOP

MOVLW

; number of bytes in holding register

MOVWF

COUNTER

WRITE_WORD_TO_HREGS

MOVFW

POSTINC0, W

; get low byte of buffer data

MOVWF

TABLAT

; present data to table latch

TBLWT+*

; write data, perform a short write

; to internal TBLWT holding register.

DECFSZ

COUNTER

; loop until buffers are full

BRA

WRITE_WORD_TO_HREGS

PIC18FXX20

DS39609A-page 70

Advance Information

2003 Microchip Technology Inc.

EXAMPLE 5-3:

WRITING TO FLASH PROGRAM MEMORY (CONTINUED)

5.5.2

WRITE VERIFY

Depending on the application, good programming
practice may dictate that the value written to the mem-
ory should be verified against the original value. This
should be used in applications where excessive writes
can stress bits near the specification limit.

5.5.3

UNEXPECTED TERMINATION OF
WRITE OPERATION

If a write is terminated by an unplanned event, such as
loss of power or an unexpected RESET, the memory
location just programmed should be verified and repro-
grammed if needed.The WRERR bit is set when a write
operation is interrupted by a MCLR Reset, or a WDT

Time-out Reset during normal operation. In these situ-
ations, users can check the WRERR bit and rewrite the
location.

5.5.4

PROTECTION AGAINST SPURIOUS
WRITES

To protect against spurious writes to FLASH program
memory, the write initiate sequence must also be fol-
lowed. See "Special Features of the CPU"
(Section 23.0) for more detail.

5.6

FLASH Program Operation During
Code Protection

See "Special Features of the CPU" (Section 23.0) for
details on code protection of FLASH program memory.

TABLE 5-2:

REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY

PROGRAM_MEMORY

BSF

EECON1,EEPGD

; point to FLASH program memory

BCF

EECON1,CFGS

; access FLASH program memory

BSF

EECON1,WREN

; enable write to memory

BCF

INTCON,GIE

; disable interrupts

MOVLW

55h

Required

MOVWF

EECON2

; write 55H

Sequence

MOVLW

AAh

MOVWF

EECON2

; write AAH

BSF

EECON1,WR

; start program (CPU stall)

NOP

BSF

INTCON,GIE

; re-enable interrupts

DECFSZ

COUNTER_HI

; loop until done

BRA PROGRAM_LOOP

BCF

EECON1,WREN

; disable write to memory

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on:

POR,

BOR

Value on
all other

RESETS

TBLPTRU

bit21

Program Memory Table Pointer Upper Byte
(TBLPTR<20:16>)

--00 0000

TBPLTRH

Program Memory Table Pointer High Byte (TBLPTR<15:8>)

0000 0000

TBLPTRL

Program Memory Table Pointer High Byte (TBLPTR<7:0>)

0000 0000

TABLAT

Program Memory Table Latch

0000 0000

INTCON

GIE/GIEH PEIE/GIEL TMR0IE

INTE

RBIE

TMR0IF

INTF

RBIF

0000 0000

EECON2

EEPROM Control Register2 (not a physical register)

EECON1

EEPGD

CFGS

FREE

WRERR

WREN

xx-0 x000

uu-0 u000

IPR2

CMIP

EEIP

BCLIP

LVDIP

TMR3IP

CCP2IP

---1 1111

PIR2

CMIF

EEIF

BCLIF

LVDIF

TMR3IF

CCP2IF

---0 0000

PIE2

CMIE

EEIE

BCLIE

LVDIE

TMR3IE

CCP2IE

---0 0000

Legend: x = unknown, u = unchanged, r = reserved, - = unimplemented, read as '0'.

Shaded cells are not used during FLASH/EEPROM access.

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DS39609A-page 71

PIC18FXX20

6.0

EXTERNAL MEMORY
INTERFACE

The External Memory Interface is a feature of the
PIC18F8X20 devices that allows the controller to
access external memory devices (such as FLASH,
EPROM, SRAM, etc.) as program or data memory.
The physical implementation of the interface uses 27
pins. These pins are reserved for external address/data
bus functions; they are multiplexed with I/O port pins on
four ports. Three I/O ports are multiplexed with the
address/data bus, while the fourth port is multiplexed
with the bus control signals. The I/O port functions are
enabled when the EBDIS bit in the MEMCON register
is set (see Register 6-1). A list of the multiplexed pins
and their functions is provided in Table 6-1.
As implemented in the PIC18F8X20 devices, the inter-
face operates in a similar manner to the external mem-
ory interface introduced on PIC18C601/801
microcontrollers. The most notable difference is that
the interface on PIC18F8X20 devices only operates in
16-bit modes. The 8-bit mode is not supported.
For a more complete discussion of the Operating modes
that use the external memory interface, refer to Section
4.1.1 ("PIC18F8X20 Program Memory Modes").

6.1

Program Memory Modes and the
External Memory Interface

As previously noted, PIC18F8X20 controllers are
capable of operating in any one of four Program Mem-
ory modes, using combinations of on-chip and exter-
nal program memory. The functions of the multiplexed
port pins depend on the Program Memory mode
selected, as well as the setting of the EBDIS bit.
In Microprocessor Mode, the external bus is always
active, and the port pins have only the external bus
function.
In Microcontroller Mode, the bus is not active and
the pins have their port functions only. Writes to the
MEMCOM register are not permitted.
In Microprocessor with Boot Block or Extended
Microcontroller Mode, the external program memory
bus shares I/O port functions on the pins. When the
device is fetching or doing Table Read/Table Write
operations on the external program memory space,
the pins will have the external bus function. If the
device is fetching and accessing internal program
memory locations only, the EBDIS control bit will
change the pins from external memory to I/O port
functions. When EBDIS = 0, the pins function as the
external bus. When EBDIS = 1, the pins function as
I/O ports.

REGISTER 6-1:

MEMCON REGISTER

Note:

The External Memory Interface is not
implemented on PIC18F6X20 (64-pin)
devices.

R/W-0

U-0

R/W-0

U-0

R/W-0

EBDIS

WAIT1

WAIT0

WM1

WM0

bit7

bit0

bit 7

EBDIS: External Bus Disable bit

= External system bus disabled, all external bus drivers are mapped as I/O ports

= External system bus enabled, and I/O ports are disabled

bit 6

Unimplemented: Read as '0'

bit 5-4

WAIT<1:0>: Table Reads and Writes Bus Cycle Wait Count bits

= Table reads and writes will wait 0 T

= Table reads and writes will wait 1 T

= Table reads and writes will wait 2 T

= Table reads and writes will wait 3 T

bit 3-2

Unimplemented: Read as '0'

bit 1-0

WM<1:0>: TBLWRT Operation with 16-bit Bus bits

= Word Write mode: TABLAT<0> and TABLAT<1> word output, WRH active when

TABLAT<1> written

= Byte Select mode: TABLAT data copied on both MS and LS Byte, WRH and (UB or LB)

will activate

= Byte Write mode: TABLAT data copied on both MS and LS Byte, WRH or WRL will activate

Legend:
R = Readable bit

W = Writable bit

U = Unimplemented bit, read as `0'

- n = Value at POR

`1' = Bit is set

`0' = Bit is cleared

x = Bit is unknown

PIC18FXX20

DS39609A-page 72

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2003 Microchip Technology Inc.

If the device fetches or accesses external memory
while EBDIS = 1, the pins will switch to external bus. If
the EBDIS bit is set by a program executing from
external memory, the action of setting the bit will be
delayed until the program branches into the internal
memory. At that time, the pins will change from
external bus to I/O ports.

When the device is executing out of internal memory
(EBDIS = 0) in Microprocessor with Boot Block mode,
or Extended Microcontroller mode, the control signals
will NOT be active. They will go to a state where the
AD<15:0> and A<19:16> are tri-state; the CE, OE,
WRH, WRL, UB and LB signals are `1'; and ALE and
BA0 are `0'.

TABLE 6-1:

PIC18F8X20 EXTERNAL BUS - I/O PORT FUNCTIONS

Name

Port

Bit

Function

RD0/AD0

PORTD

bit0 Input/Output or System Bus Address bit 0 or Data bit 0.

RD1/AD1

PORTD

bit1 Input/Output or System Bus Address bit 1 or Data bit 1.

RD2/AD2

PORTD

bit2 Input/Output or System Bus Address bit 2 or Data bit 2.

RD3/AD3

PORTD

bit3 Input/Output or System Bus Address bit 3 or Data bit 3.

RD4/AD4

PORTD

bit4 Input/Output or System Bus Address bit 4 or Data bit 4.

RD5/AD5

PORTD

bit5 Input/Output or System Bus Address bit 5 or Data bit 5.

RD6/AD6

PORTD

bit6 Input/Output or System Bus Address bit 6 or Data bit 6.

RD7/AD7

PORTD

bit7 Input/Output or System Bus Address bit 7 or Data bit 7.

RE0/AD8

PORTE

bit0 Input/Output or System Bus Address bit 8 or Data bit 8.

RE1/AD9

PORTE

bit1 Input/Output or System Bus Address bit 9 or Data bit 9.

RE2/AD10

PORTE

bit2 Input/Output or System Bus Address bit 10 or Data bit 10.

RE3/AD11

PORTE

bit3 Input/Output or System Bus Address bit 11 or Data bit 11.

RE4/AD12

PORTE

bit4 Input/Output or System Bus Address bit 12 or Data bit 12.

RE5/AD13

PORTE

bit5 Input/Output or System Bus Address bit 13 or Data bit 13.

RE6/AD14

PORTE

bit6 Input/Output or System Bus Address bit 14 or Data bit 14.

RE7/AD15

PORTE

bit7 Input/Output or System Bus Address bit 15 or Data bit 15.

RH0/A16

PORTH

bit0 Input/Output or System Bus Address bit 16.

RH1/A17

PORTH

bit1 Input/Output or System Bus Address bit 17.

RH2/A18

PORTH

bit2 Input/Output or System Bus Address bit 18.

RH3/A19

PORTH

bit3 Input/Output or System Bus Address bit 19.

RJ0/ALE

PORTJ

bit0 Input/Output or System Bus Address Latch Enable (ALE) Control pin.

RJ1/OE

PORTJ

bit1 Input/Output or System Bus Output Enable (OE) Control pin.

RJ2/WRL

PORTJ

bit2 Input/Output or System Bus Write Low (WRL) Control pin.

RJ3/WRH

PORTJ

bit3 Input/Output or System Bus Write High (WRH) Control pin.

RJ4/BA0

PORTJ

bit4 Input/Output or System Bus Byte Address bit 0.

RJ5/CE

PORTJ

bit5 Input/Output or System Bus Chip Enable (CE) Control pin.

RJ6/LB

PORTJ

bit6 Input/Output or System Bus Lower Byte Enable (LB) Control pin.

RJ7/UB

PORTJ

bit7 Input/Output or System Bus Upper Byte Enable (UB) Control pin.

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PIC18FXX20

6.2

16-bit Mode

The External Memory Interface implemented in
PIC18F8X20 devices operates only in 16-bit mode.
The mode selection is not software configurable, but is
programmed via the configuration bits.
The WM<1:0> bits in the MEMCON register determine
three types of connections in 16-bit mode. They are
referred to as:
� 16-bit Byte Write
� 16-bit Word Write
� 16-bit Byte Select
These three different configurations allow the designer
maximum flexibility in using 8-bit and 16-bit memory
devices.
For all 16-bit modes, the Address Latch Enable (ALE)
pin indicates that the address bits A<15:0> are avail-
able on the External Memory Interface bus. Following
the address latch, the output enable signal (OE) will
enable both bytes of program memory at once to form
a 16-bit instruction word. The Chip Enable signal (CE)
is active at any time that the microcontroller accesses
external memory, whether reading or writing; it is inac-
tive (asserted high) whenever the device is in SLEEP
mode.

In Byte Select mode, JEDEC standard FLASH memo-
ries will require BA0 for the byte address line, and one
I/O line to select between Byte and Word mode. The
other 16-bit modes do not need BA0. JEDEC standard
static RAM memories will use the UB or LB signals for
byte selection.

6.2.1

16-BIT BYTE WRITE MODE

Figure 6-1 shows an example of 16-bit Byte Write
mode for PIC18F8X20 devices. This mode is used for
two separate 8-bit memories connected for 16-bit oper-
ation. This generally includes basic EPROM and
FLASH devices. It allows Table Writes to byte-wide
external memories.
During a TBLWT instruction cycle, the TABLAT data is
presented on the upper and lower bytes of the
AD15:AD0 bus. The appropriate WRH or WRL control
line is strobed on the LSb of the TBLPTR.

FIGURE 6-1:

16-BIT BYTE WRITE MODE EXAMPLE

AD<7:0>

A<19:16>

ALE

D<15:8>

373

A<x:0>

D<7:0>

A<19:0>

A<x:0>

D<7:0>

373

WRH

(1)

Note 1: This signal only applies to Table Writes. See Section 5.1 (Table Reads and Writes).

WRL

D<7:0>

(LSB)

(MSB)

PIC18F8X20

D<7:0>

AD<15:8>

Address Bus
Data Bus
Control Lines

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PIC18FXX20

7.0

DATA EEPROM MEMORY

The Data EEPROM is readable and writable during
normal operation over the entire V

range. The data

memory is not directly mapped in the register file
space. Instead, it is indirectly addressed through the
Special Function Registers (SFR).
There are five SFRs used to read and write the
program and data EEPROM memory. These registers
are:
� EECON1
� EECON2
� EEDATA
� EEADRH
� EEADR
The EEPROM data memory allows byte read and write.
When interfacing to the data memory block, EEDATA
holds the 8-bit data for read/write. EEADR and
EEADRH hold the address of the EEPROM location
being accessed. These devices have 1024 bytes of
data EEPROM with an address range from 00h to
3FFh.
The EEPROM data memory is rated for high
erase/write cycles. A byte write automatically erases
the location and writes the new data
(erase-before-write). The write time is controlled by an
on-chip timer. The write time will vary with voltage and
temperature, as well as from chip to chip. Please refer
to parameter D122 (Electrical Characteristics,
Section 26.0) for exact limits.

7.1

EEADR and EEADRH

The address register pair can address up to a maxi-
mum of 1024 bytes of data EEPROM. The two MSbits
of the address are stored in EEADRH, while the
remaining eight LSbits are stored in EEADR. The six
Most Significant bits of EEADRH are unused, and are
read as `0'.

7.2

EECON1 and EECON2 Registers

EECON1 is the control register for EEPROM memory
accesses.
EECON2 is not a physical register. Reading EECON2
will read all `0's. The EECON2 register is used
exclusively in the EEPROM write sequence.
Control bits RD and WR initiate read and write opera-
tions, respectively. These bits cannot be cleared, only
set, in software. They are cleared in hardware at the
completion of the read or write operation. The inability
to clear the WR bit in software prevents the accidental
or premature termination of a write operation.
The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is clear. The WRERR bit is
set when a write operation is interrupted by a MCLR
Reset, or a WDT Time-out Reset during normal opera-
tion. In these situations, the user can check the
WRERR bit and rewrite the location. It is necessary to
reload the data and address registers (EEDATA and
EEADR), due to the RESET condition forcing the
contents of the registers to zero.

Note:

Interrupt flag bit, EEIF in the PIR2 register,
is set when write is complete. It must be
cleared in software.

PIC18FXX20

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REGISTER 7-1:

EECON1 REGISTER (ADDRESS FA6h)

R/W-x

U-0

R/W-0

R/W-x

R/W-0

R/S-0

EEPGD

CFGS

FREE

WRERR

WREN

bit 7

bit 0

bit 7

EEPGD: FLASH Program/Data EEPROM Memory Select bit

= Access FLASH Program memory

= Access Data EEPROM memory

bit 6

CFGS: FLASH Program/Data EEPROM or Configuration Select bit

= Access Configuration or Calibration registers

= Access FLASH Program or Data EEPROM memory

bit 5

Unimplemented: Read as '0'

bit 4

FREE: FLASH Row Erase Enable bit

= Erase the program memory row addressed by TBLPTR on the next WR command

(cleared by completion of erase operation)

= Perform write only

bit 3

WRERR: FLASH Program/Data EEPROM Error Flag bit

= A write operation is prematurely terminated

(any MCLR or any WDT Reset during self-timed programming in normal operation)

= The write operation completed

Note: When a WRERR occurs, the EEPGD or FREE bits are not cleared. This allows tracing

of the error condition.

bit 2

WREN: FLASH Program/Data EEPROM Write Enable bit

= Allows write cycles to FLASH Program/Data EEPROM

= Inhibits write cycles to FLASH Program/Data EEPROM

bit 1

WR: Write Control bit

= Initiates a Data EEPROM erase/write cycle, or a program memory erase cycle or write cycle.

(The operation is self-timed and the bit is cleared by hardware once write is complete. The
WR bit can only be set (not cleared) in software.)

= Write cycle to the EEPROM is complete

bit 0

RD: Read Control bit

= Initiates an EEPROM read

(Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared)
in software. RD bit cannot be set when EEPGD = 1.)

= Does not initiate an EEPROM read

Legend:
R = Readable bit

W = Writable bit

U = Unimplemented bit, read as `0'

- n = Value at POR

`1' = Bit is set

`0' = Bit is cleared

x = Bit is unknown

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DS39609A-page 81

PIC18FXX20

7.3

Reading the Data EEPROM
Memory

To read a data memory location, the user must write the
address to the EEADRH:EEADR register pair, clear the
EEPGD control bit (EECON1<7>), clear the CFGS

control bit (EECON1<6>), and then set the RD control
bit (EECON1<0>). The data is available for the very
next instruction cycle; therefore, the EEDATA register
can be read by the next instruction. EEDATA will hold
this value until another read operation, or until it is
written to by the user (during a write operation).

EXAMPLE 7-1:

DATA EEPROM READ

7.4

Writing to the Data EEPROM
Memory

To write an EEPROM data location, the address must
first be written to the EEADRH:EEADR register pair
and the data written to the EEDATA register. Then the
sequence in Example 7-2 must be followed to initiate
the write cycle.
The write will not initiate if the above sequence is not
exactly followed (write 55h to EECON2, write AAh to
EECON2, then set WR bit) for each byte. It is strongly
recommended that interrupts be disabled during this
code segment.
Additionally, the WREN bit in EECON1 must be set to
enable writes. This mechanism prevents accidental
writes to data EEPROM due to unexpected code exe-

cution (i.e., runaway programs). The WREN bit should
be kept clear at all times, except when updating the
EEPROM. The WREN bit is not cleared by hardware
After a write sequence has been initiated, EECON1,
EEADRH, EEADR and EEDATA cannot be modified.
The WR bit will be inhibited from being set unless the
WREN bit is set. The WREN bit must be set on a pre-
vious instruction. Both WR and WREN cannot be set
with the same instruction.
At the completion of the write cycle, the WR bit is
cleared in hardware and the EEPROM Write Complete
Interrupt Flag bit (EEIF) is set. The user may either
enable this interrupt, or poll this bit. EEIF must be
cleared by software.

EXAMPLE 7-2:

DATA EEPROM WRITE

MOVLW

DATA_EE_ADDRH

;

MOVWF

EEADRH

; Upper bits of Data Memory Address to read

MOVLW

DATA_EE_ADDR

;

MOVWF

EEADR

; Lower bits of Data Memory Address to read

BCF

EECON1, EEPGD

; Point to DATA memory

BCF

EECON1, CFGS

; Access EEPROM

BSF

EECON1, RD

; EEPROM Read

MOVF

EEDATA, W

; W = EEDATA

MOVLW

DATA_EE_ADDRH

;

MOVWF

EEADRH

; Upper bits of Data Memory Address to write

MOVLW

DATA_EE_ADDR

;

MOVWF

EEADR

; Lower bits of Data Memory Address to write

MOVLW

DATA_EE_DATA

;

MOVWF

EEDATA

; Data Memory Value to write

BCF

EECON1, EEPGD

; Point to DATA memory

BCF

EECON1,CFGS

; Access EEPROM

BSF

EECON1, WREN

; Enable writes

BCF

INTCON, GIE

; Disable Interrupts

MOVLW

55h

;

Required

MOVWF

EECON2

; Write 55h

Sequence

MOVLW

AAh

;

MOVWF

EECON2

; Write AAh

BSF

EECON1, WR

; Set WR bit to begin write

BSF

INTCON, GIE

; Enable Interrupts

; User code execution

BCF

EECON1, WREN

; Disable writes on write complete (EEIF set)

PIC18FXX20

DS39609A-page 82

Advance Information

2003 Microchip Technology Inc.

7.5

Write Verify

7.6

Protection Against Spurious Write

There are conditions when the device may not want to
write to the data EEPROM memory. To protect against
spurious EEPROM writes, various mechanisms have
been built-in. On power-up, the WREN bit is cleared.
Also, the Power-up Timer (72 ms duration) prevents
EEPROM write.
The write initiate sequence and the WREN bit together
help prevent an accidental write during brown-out,
power glitch, or software malfunction.

7.7

Operation During Code Protect

Data EEPROM memory has its own code protect
mechanism. External Read and Write operations are
disabled if either of these mechanisms are enabled.
The microcontroller itself can both read and write to the
internal Data EEPROM, regardless of the state of the
code protect configuration bit. Refer to "Special
Features of the CPU" (Section 23.0) for additional
information.

7.8

Using the Data EEPROM

The data EEPROM is a high endurance, byte address-
able array that has been optimized for the storage of
frequently changing information (e.g., program vari-
ables or other data that are updated often). Frequently
changing values will typically be updated more often
than specification D124. If this is not the case, an array
refresh must be performed. For this reason, variables
that change infrequently (such as constants, IDs, cali-
bration, etc.) should be stored in FLASH program
memory.
A simple data EEPROM refresh routine is shown in
Example 7-3.

EXAMPLE 7-3:

DATA EEPROM REFRESH ROUTINE

Note:

If data EEPROM is only used to store con-
stants and/or data that changes rarely, an
array refresh is likely not required. See
specification D124.

clrf

EEADR

; Start at address 0

clrf

EEADRH

;

bcf

EECON1,CFGS

; Set for memory

bcf

EECON1,EEPGD

; Set for Data EEPROM

bcf

INTCON,GIE

; Disable interrupts

bsf

EECON1,WREN

; Enable writes

Loop

; Loop to refresh array

bsf

EECON1,RD

; Read current address

movlw

55h

;

movwf

EECON2

; Write 55h

movlw

AAh

;

movwf

EECON2

; Write AAh

bsf

EECON1,WR

; Set WR bit to begin write

btfsc

EECON1,WR

; Wait for write to complete

bra

$-2

incfsz EEADR,F

; Increment address

bra

Loop

; Not zero, do it again

incfsz EEADRH, F

; Increment the high address

bra

Loop

; Not zero, do it again

bcf

EECON1,WREN

; Disable writes

bsf

INTCON,GIE

; Enable interrupts

2003 Microchip Technology Inc.

Advance Information

DS39609A-page 85

PIC18FXX20

8.0

8 X 8 HARDWARE MULTIPLIER

8.1

Introduction

An 8 x 8 hardware multiplier is included in the ALU of
the PIC18FXX20 devices. By making the multiply a
hardware operation, it completes in a single instruction
cycle. This is an unsigned multiply that gives a 16-bit
result. The result is stored in the 16-bit product register
pair (PRODH:PRODL). The multiplier does not affect
any flags in the ALUSTA register.
Making the 8 x 8 multiplier execute in a single cycle
gives the following advantages:
� Higher computational throughput
� Reduces code size requirements for multiply

algorithms

The performance increase allows the device to be used
in applications previously reserved for Digital Signal
Processors.
Table 8-1 shows a performance comparison between
enhanced devices using the single cycle hardware mul-
tiply, and performing the same function without the
hardware multiply.

8.2

Operation

Example 8-1 shows the sequence to do an 8 x 8
unsigned multiply. Only one instruction is required
when one argument of the multiply is already loaded in
the WREG register.
Example 8-2 shows the sequence to do an 8 x 8 signed
multiply. To account for the sign bits of the arguments,
each argument's Most Significant bit (MSb) is tested
and the appropriate subtractions are done.

EXAMPLE 8-1:

8 x 8 UNSIGNED
MULTIPLY ROUTINE

EXAMPLE 8-2:

8 x 8 SIGNED MULTIPLY
ROUTINE

TABLE 8-1:

PERFORMANCE COMPARISON

MOVF ARG1, W ;

MULWF ARG2 ; ARG1 * ARG2 ->

; PRODH:PRODL

MOVF ARG1, W

MULWF ARG2 ; ARG1 * ARG2 ->

; PRODH:PRODL

BTFSC ARG2, SB ; Test Sign Bit

SUBWF PRODH, F ; PRODH = PRODH

; - ARG1

MOVF ARG2, W

BTFSC ARG1, SB ; Test Sign Bit

SUBWF PRODH, F ; PRODH = PRODH

; - ARG2

Routine

Multiply Method

Program

Memory
(Words)

Cycles

(Max)

Time

@ 40 MHz

@ 10 MHz

@ 4 MHz

8 x 8 unsigned

Without hardware multiply

6.9

祍

27.6

祍

Hardware multiply

100 ns

400 ns

祍

8 x 8 signed

Without hardware multiply

9.1

祍

36.4

祍

Hardware multiply

600 ns

2.4

祍

16 x 16 unsigned

Without hardware multiply

242

24.2

祍

96.8

祍

242

祍

Hardware multiply

2.8

祍

11.2

祍

16 x 16 signed

Without hardware multiply

254

25.4

祍

102.6

祍

254

祍

Hardware multiply

4.0

祍

16.0

祍

PIC18FXX20

DS39609A-page 86

Advance Information

2003 Microchip Technology Inc.

Example 8-3 shows the sequence to do a 16 x 16
unsigned multiply. Equation 8-1 shows the algorithm
that is used. The 32-bit result is stored in four registers,
RES3:RES0.

EQUATION 8-1:

16 x 16 UNSIGNED
MULTIPLICATION
ALGORITHM

EXAMPLE 8-3:

16 x 16 UNSIGNED
MULTIPLY ROUTINE

Example 8-4 shows the sequence to do a 16 x 16
signed multiply. Equation 8-2 shows the algorithm
used. The 32-bit result is stored in four registers,
RES3:RES0. To account for the sign bits of the argu-
ments, each argument pairs Most Significant bit (MSb)
is tested and the appropriate subtractions are done.

EQUATION 8-2:

16 x 16 SIGNED
MULTIPLICATION
ALGORITHM

EXAMPLE 8-4:

16 x 16 SIGNED
MULTIPLY ROUTINE

MOVF

ARG1L, W

MULWF

ARG2L

; ARG1L * ARG2L ->

; PRODH:PRODL

MOVFF

PRODH,

RES1

;

MOVFF

PRODL,

RES0

;

MOVF

ARG1H,

MULWF

ARG2H

; ARG1H * ARG2H ->

; PRODH:PRODL

MOVFF

PRODH,

RES3

;

MOVFF

PRODL,

RES2

;

MOVF

ARG1L,

MULWF

ARG2H

; ARG1L * ARG2H ->

; PRODH:PRODL

MOVF

PRODL,

;

ADDWF

RES1,

; Add cross

MOVF

PRODH,

; products

ADDWFC

RES2,

;

CLRF

WREG

;

ADDWFC

RES3,

;

MOVF

ARG1H,

;

MULWF

ARG2L

; ARG1H * ARG2L ->

; PRODH:PRODL

MOVF

PRODL,

;

ADDWF

RES1,

; Add cross

MOVF

PRODH,

; products

ADDWFC

RES2,

;

CLRF

WREG

;

ADDWFC

RES3,

;

RES3:RES0

ARG1H:ARG1L

� ARG2H:ARG2L

(ARG1H

� ARG2H � 2

) +

(ARG1H

� ARG2L � 2

) +

(ARG1L

� ARG2H � 2

) +

(ARG1L

� ARG2L)

MOVF

ARG1L,

MULWF

ARG2L

; ARG1L * ARG2L ->

; PRODH:PRODL

MOVFF

PRODH,

RES1

;

MOVFF

PRODL,

RES0

;

MOVF

ARG1H,

MULWF

ARG2H

; ARG1H * ARG2H ->

; PRODH:PRODL

MOVFF

PRODH,

RES3

;

MOVFF

PRODL,

RES2

;

MOVF

ARG1L,

MULWF

ARG2H

; ARG1L * ARG2H ->

; PRODH:PRODL

MOVF

PRODL,

;

ADDWF

RES1,

; Add cross

MOVF

PRODH,

; products

ADDWFC

RES2,

;

CLRF

WREG

;

ADDWFC

RES3,

;

MOVF

ARG1H,

;

MULWF

ARG2L

; ARG1H * ARG2L ->

; PRODH:PRODL

MOVF

PRODL,

W ;

ADDWF

RES1,

; Add cross

MOVF

PRODH,

; products

ADDWFC RES2,

;

CLRF

WREG

;

ADDWFC

RES3,

;

BTFSS

ARG2H,

; ARG2H:ARG2L neg?

BRA

SIGN_ARG1

; no, check ARG1

MOVF

ARG1L,

;

SUBWF

RES2

;

MOVF

ARG1H,

;

SUBWFB

RES3

;

SIGN_ARG1

BTFSS

ARG1H,

; ARG1H:ARG1L neg?

BRA

CONT_CODE

; no, done

MOVF

ARG2L,

;

SUBWF

RES2

;

MOVF

ARG2H,

;

SUBWFB

RES3

;

CONT_CODE

RES3:RES0

ARG1H:ARG1L

� ARG2H:ARG2L

(ARG1H

� ARG2H � 2

) +

(ARG1H

� ARG2L � 2

) +

(ARG1L

� ARG2H � 2

) +

(ARG1L

� ARG2L)+

(-1

� ARG2H<7> � ARG1H:ARG1L � 2

) +

(-1

� ARG1H<7> � ARG2H:ARG2L � 2

)

2003 Microchip Technology Inc.

Advance Information

DS39609A-page 87

PIC18FXX20

9.0

INTERRUPTS

The PIC18FXX20 devices have multiple interrupt
sources and an interrupt priority feature that allows
each interrupt source to be assigned a high or a low pri-
ority level. The high priority interrupt vector is at
000008h, while the low priority interrupt vector is at
000018h. High priority interrupt events will override any
low priority interrupts that may be in progress.
There are thirteen registers which are used to control
interrupt operation. They are:
� RCON
� INTCON
� INTCON2
� INTCON3
� PIR1, PIR2, PIR3
� PIE1, PIE2, PIE3
� IPR1, IPR2, IPR3
It is recommended that the Microchip header files, sup-
plied with MPLAB

�

IDE, be used for the symbolic bit

names in these registers. This allows the assem-
bler/compiler to automatically take care of the
placement of these bits within the specified register.
Each interrupt source has three bits to control its
operation. The functions of these bits are:
� Flag bit to indicate that an interrupt event

occurred

� Enable bit that allows program execution to

branch to the interrupt vector address when the
flag bit is set

� Priority bit to select high priority or low priority
The interrupt priority feature is enabled by setting the
IPEN bit (RCON<7>). When interrupt priority is
enabled, there are two bits which enable interrupts glo-
bally. Setting the GIEH bit (INTCON<7>) enables all
interrupts that have the priority bit set. Setting the GIEL
bit (INTCON<6>) enables all interrupts that have the
priority bit cleared. When the interrupt flag, enable bit
and appropriate global interrupt enable bit are set, the
interrupt will vector immediately to address 000008h or
000018h, depending on the priority level. Individual
interrupts can be disabled through their corresponding
enable bits.

When the IPEN bit is cleared (default state), the inter-
rupt priority feature is disabled and interrupts are com-
patible with PICmicro

�

mid-range devices. In

Compatibility mode, the interrupt priority bits for each
source have no effect. INTCON<6> is the PEIE bit,
which enables/disables all peripheral interrupt sources.
INTCON<7> is the GIE bit, which enables/disables all
interrupt sources. All interrupts branch to address
000008h in Compatibility mode.
When an interrupt is responded to, the Global Interrupt
Enable bit is cleared to disable further interrupts. If the
IPEN bit is cleared, this is the GIE bit. If interrupt priority
levels are used, this will be either the GIEH or GIEL bit.
High priority interrupt sources can interrupt a low
priority interrupt.
The return address is pushed onto the stack and the
PC is loaded with the interrupt vector address
(000008h or 000018h). Once in the Interrupt Service
Routine, the source(s) of the interrupt can be deter-
mined by polling the interrupt flag bits. The interrupt
flag bits must be cleared in software before re-enabling
interrupts to avoid recursive interrupts.
The "return from interrupt" instruction, RETFIE, exits
the interrupt routine and sets the GIE bit (GIEH or GIEL
if priority levels are used), which re-enables interrupts.
For external interrupt events, such as the INT pins or
the PORTB input change interrupt, the interrupt latency
will be three to four instruction cycles. The exact
latency is the same for one or two-cycle instructions.
Individual interrupt flag bits are set, regardless of the
status of their corresponding enable bit or the GIE bit.

2003 Microchip Technology Inc.

Advance Information

DS39609A-page 89

PIC18FXX20

9.1

INTCON Registers

The INTCON Registers are readable and writable reg-
isters, which contain various enable, priority and flag
bits.

REGISTER 9-1:

INTCON REGISTER

Note:

Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit. User software should ensure
the appropriate interrupt flag bits are clear
prior to enabling an interrupt. This feature
allows for software polling.

R/W-0

R/W-x

GIE/GIEH

PEIE/GIEL

TMR0IE

INT0IE

RBIE

TMR0IF

INT0IF

RBIF

bit 7

bit 0

bit 7

GIE/GIEH: Global Interrupt Enable bit
When IPEN (RCON<7>) = 0:
1

= Enables all unmasked interrupts

= Disables all interrupts

When IPEN (RCON<7>) = 1:
1

= Enables all high priority interrupts

= Disables all interrupts

bit 6

PEIE/GIEL: Peripheral Interrupt Enable bit
When IPEN (RCON<7>) = 0:
1

= Enables all unmasked peripheral interrupts

= Disables all peripheral interrupts

When IPEN (RCON<7>) = 1:
1

= Enables all low priority peripheral interrupts

= Disables all low priority peripheral interrupts

bit 5

TMR0IE: TMR0 Overflow Interrupt Enable bit
1

= Enables the TMR0 overflow interrupt

= Disables the TMR0 overflow interrupt

bit 4

INT0IE: INT0 External Interrupt Enable bit
1

= Enables the INT0 external interrupt

= Disables the INT0 external interrupt

bit 3

RBIE: RB Port Change Interrupt Enable bit

= Enables the RB port change interrupt

= Disables the RB port change interrupt

bit 2

TMR0IF: TMR0 Overflow Interrupt Flag bit
1

= TMR0 register has overflowed (must be cleared in software)

= TMR0 register did not overflow

bit 1

INT0IF: INT0 External Interrupt Flag bit
1

= The INT0 external interrupt occurred (must be cleared in software)

= The INT0 external interrupt did not occur

bit 0

RBIF: RB Port Change Interrupt Flag bit
1

= At least one of the RB7:RB4 pins changed state (must be cleared in software)

= None of the RB7:RB4 pins have changed state

Note:

A mismatch condition will continue to set this bit. Reading PORTB will end the
mismatch condition and allow the bit to be cleared.

Legend:
R = Readable bit

W = Writable bit

U = Unimplemented bit, read as `0'

- n = Value at POR

`1' = Bit is set

`0' = Bit is cleared

x = Bit is unknown

2003 Microchip Technology Inc.

Advance Information

DS39609A-page 91

PIC18FXX20

REGISTER 9-3:

INTCON3 REGISTER

R/W-1

R/W-0

INT2IP

INT1IP

INT3IE

INT2IE

INT1IE

INT3IF

INT2IF

INT1IF

bit 7

bit 0

bit 7

INT2IP: INT2 External Interrupt Priority bit

= High priority

= Low priority

bit 6

INT1IP: INT1 External Interrupt Priority bit

= High priority

= Low priority

bit 5

INT3IE: INT3 External Interrupt Enable bit

= Enables the INT3 external interrupt

= Disables the INT3 external interrupt

bit 4

INT2IE: INT2 External Interrupt Enable bit

= Enables the INT2 external interrupt

= Disables the INT2 external interrupt

bit 3

INT1IE: INT1 External Interrupt Enable bit

= Enables the INT1 external interrupt

= Disables the INT1 external interrupt

bit 2

INT3IF: INT3 External Interrupt Flag bit

= The INT3 external interrupt occurred (must be cleared in software)

= The INT3 external interrupt did not occur

bit 1

INT2IF: INT2 External Interrupt Flag bit

= The INT2 external interrupt occurred (must be cleared in software)

= The INT2 external interrupt did not occur

bit 0

INT1IF: INT1 External Interrupt Flag bit

= The INT1 external interrupt occurred (must be cleared in software)

= The INT1 external interrupt did not occur

Legend:
R = Readable bit

W = Writable bit

U = Unimplemented bit, read as `0'

- n = Value at POR

`1' = Bit is set

`0' = Bit is cleared

x = Bit is unknown

Note:

Interrupt flag bits are set when an interrupt condition occurs, regardless of the state
of its corresponding enable bit or the global enable bit. User software should ensure
the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature
allows for software polling.

PIC18FXX20

DS39609A-page 92

Advance Information

2003 Microchip Technology Inc.

9.2

PIR Registers

The PIR registers contain the individual flag bits for the
peripheral interrupts. Due to the number of peripheral
interrupt sources, there are three Peripheral Interrupt
Flag Registers (PIR1, PIR2 and PIR3).

REGISTER 9-4:

PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1

Note 1: Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>).

2: User software should ensure the appropriate

interrupt flag bits are cleared prior to enabling
an interrupt, and after servicing that interrupt.

R/W-0

R-0

R/W-0

PSPIF

(1)

ADIF

RC1IF

TX1IF

SSPIF

CCP1IF

TMR2IF

TMR1IF

bit

bit 0

bit 7

PSPIF: Parallel Slave Port Read/Write Interrupt Flag bit

(1)

= A read or a write operation has taken place (must be cleared in software)

= No read or write has occurred

bit 6

ADIF: A/D Converter Interrupt Flag bit
1

= An A/D conversion completed (must be cleared in software)

= The A/D conversion is not complete

bit 5

RC1IF: USART1 Receive Interrupt Flag bit
1

= The USART1 receive buffer, RCREG, is full (cleared when RCREG is read)

= The USART1 receive buffer is empty

bit 4

TX1IF: USART Transmit Interrupt Flag bit
1

= The USART1 transmit buffer, TXREG, is empty (cleared when TXREG is written)

= The USART1 transmit buffer is full

bit 3

SSPIF: Master Synchronous Serial Port Interrupt Flag bit
1

= The transmission/reception is complete (must be cleared in software)

= Waiting to transmit/receive

bit 2

CCP1IF: CCP1 Interrupt Flag bit
Capture mode:
1

= A TMR1 register capture occurred (must be cleared in software)

= No TMR1 register capture occurred

Compare mode:
1

= A TMR1 register compare match occurred (must be cleared in software)

= No TMR1 register compare match occurred

PWM mode:
Unused in this mode

bit 1

TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1

= TMR2 to PR2 match occurred (must be cleared in software)

= No TMR2 to PR2 match occurred

bit 0

TMR1IF: TMR1 Overflow Interrupt Flag bit
1

= TMR1 register overflowed (must be cleared in software)

= MR1 register did not overflow

Note 1:

Enabled only in Microcontroller mode for PIC18F8X20 devices.

Legend:
R = Readable bit

W = Writable bit

U = Unimplemented bit, read as `0'

- n = Value at POR

`1' = Bit is set

`0' = Bit is cleared

x = Bit is unknown

2003 Microchip Technology Inc.

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DS39609A-page 95

PIC18FXX20

9.3

PIE Registers

The PIE registers contain the individual enable bits for
the peripheral interrupts. Due to the number of periph-
eral interrupt sources, there are three Peripheral Inter-
rupt Enable Registers (PIE1, PIE2 and PIE3). When
the IPEN bit (RCON<7>) is `0', the PEIE bit must be set
to enable any of these peripheral interrupts.

REGISTER 9-7:

PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1

R/W-0

PSPIE

(1)

ADIE

RC1IE

TX1IE

SSPIE

CCP1IE

TMR2IE

TMR1IE

bit 7

bit 0

bit 7

PSPIE: Parallel Slave Port Read/Write Interrupt Enable bit

(1)

= Enables the PSP read/write interrupt

= Disables the PSP read/write interrupt

bit 6

ADIE: A/D Converter Interrupt Enable bit

= Enables the A/D interrupt

= Disables the A/D interrupt

bit 5

RC1IE: USART1 Receive Interrupt Enable bit

= Enables the USART1 receive interrupt

= Disables the USART1 receive interrupt

bit 4

TX1IE: USART1 Transmit Interrupt Enable bit

= Enables the USART1 transmit interrupt

= Disables the USART1 transmit interrupt

bit 3

SSPIE: Master Synchronous Serial Port Interrupt Enable bit

= Enables the MSSP interrupt

= Disables the MSSP interrupt

bit 2

CCP1IE: CCP1 Interrupt Enable bit

= Enables the CCP1 interrupt

= Disables the CCP1 interrupt

bit 1

TMR2IE: TMR2 to PR2 Match Interrupt Enable bit

= Enables the TMR2 to PR2 match interrupt

= Disables the TMR2 to PR2 match interrupt

bit 0

TMR1IE: TMR1 Overflow Interrupt Enable bit

= Enables the TMR1 overflow interrupt

= Disables the TMR1 overflow interrupt

Note 1:

Enabled only in Microcontroller mode for PIC18F8X20 devices.

Legend:
R = Readable bit

W = Writable bit

U = Unimplemented bit, read as `0'

- n = Value at POR

`1' = Bit is set

`0' = Bit is cleared

x = Bit is unknown

PIC18FXX20

DS39609A-page 102

Advance Information

2003 Microchip Technology Inc.

9.6

INT0 Interrupt

External interrupts on the RB0/INT0, RB1/INT1,
RB2/INT2 and RB3/INT3 pins are edge-triggered:
either rising, if the corresponding INTEDGx bit is set in
the INTCON2 register, or falling, if the INTEDGx bit is
clear. When a valid edge appears on the RBx/INTx pin,
the corresponding flag bit, INTxF, is set. This interrupt
can be disabled by clearing the corresponding enable
bit, INTxE. Flag bit, INTxF, must be cleared in software
in the Interrupt Service Routine before re-enabling the
interrupt. All external interrupts (INT0, INT1, INT2 and
INT3) can wake-up the processor from SLEEP, if bit
INTxIE was set prior to going into SLEEP. If the global
interrupt enable bit GIE is set, the processor will branch
to the interrupt vector following wake-up.
The interrupt priority for INT, INT2 and INT3 is deter-
mined by the value contained in the interrupt priority
bits: INT1IP (INTCON3<6>), INT2IP (INTCON3<7>)
and INT3IP (INTCON2<1>). There is no priority bit
associated with INT0; it is always a high priority
interrupt source.

9.7

TMR0 Interrupt

In 8-bit mode (which is the default), an overflow in the
TMR0 register (FFh

00h) will set flag bit TMR0IF. In

16-bit mode, an overflow in the TMR0H:TMR0L regis-
ters (FFFFh

0000h) will set flag bit TMR0IF. The

interrupt can be enabled/disabled by setting/clearing
enable bit, TMR0IE (INTCON<5>). Interrupt priority for
Timer0 is determined by the value contained in the
interrupt priority bit, TMR0IP (INTCON2<2>). See
Section 11.0 for further details on the Timer0 module.

9.8

PORTB Interrupt-on-Change

An input change on PORTB<7:4> sets flag bit RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit, RBIE (INTCON<3>).
Interrupt priority for PORTB interrupt-on-change is
determined by the value contained in the interrupt
priority bit, RBIP (INTCON2<0>).

9.9

Context Saving During Interrupts

During an interrupt, the return PC value is saved on the
stack. Additionally, the WREG, STATUS and BSR regis-
ters are saved on the fast return stack. If a fast return
from interrupt is not used (See Section 4.3), the user
may need to save the WREG, STATUS and BSR regis-
ters in software. Depending on the user's application,
other registers may also need to be saved. Example 9-1
saves and restores the WREG, STATUS and BSR
registers during an Interrupt Service Routine.

EXAMPLE 9-1:

SAVING STATUS, WREG AND BSR REGISTERS IN RAM

MOVWF

W_TEMP

; W_TEMP is in virtual bank

MOVFF

STATUS, STATUS_TEMP

; STATUS_TEMP located anywhere

MOVFF

BSR,

BSR_TEMP

; BSR located anywhere

;

; USER ISR CODE

;

MOVFF

BSR_TEMP,

BSR

; Restore BSR

MOVF

W_TEMP,

; Restore WREG

MOVFF

STATUS_TEMP,STATUS

; Restore STATUS

2003 Microchip Technology Inc.

Advance Information

DS39609A-page 103

PIC18FXX20

10.0 I/O PORTS

Depending on the device selected, there are either
seven or nine I/O ports available on PIC18FXX20
devices. Some of their pins are multiplexed with one or
more alternate functions from the other peripheral fea-
tures on the device. In general, when a peripheral is
enabled, that pin may not be used as a general
purpose I/O pin.
Each port has three registers for its operation. These
registers are:
� TRIS register (data direction register)
� PORT register (reads the levels on the pins of the

device)

� LAT register (output latch)
The data latch (LAT register) is useful for read-
modify-write operations on the value that the I/O pins
are driving.
A simplified version of a generic I/O port and its
operation is shown in Figure 10-1.

FIGURE 10-1:

SIMPLIFIED BLOCK
DIAGRAM OF
PORT/LAT/TRIS
OPERATION

10.1

PORTA, TRISA and LATA
Registers

PORTA is a 7-bit wide, bi-directional port. The corre-
sponding Data Direction register is TRISA. Setting a
TRISA bit (= 1) will make the corresponding PORTA pin
an input (i.e., put the corresponding output driver in a
High-Impedance mode). Clearing a TRISA bit (= 0) will
make the corresponding PORTA pin an output (i.e., put
the contents of the output latch on the selected pin).
Reading the PORTA register reads the status of the
pins, whereas writing to it will write to the port latch.
The Data Latch register (LATA) is also memory
mapped. Read-modify-write operations on the LATA
register, read and write the latched output value for
PORTA.
The RA4 pin is multiplexed with the Timer0 module
clock input to become the RA4/T0CKI pin. The
RA4/T0CKI pin is a Schmitt Trigger input and an open
drain output. All other RA port pins have TTL input
levels and full CMOS output drivers.
The RA6 pin is only enabled as a general I/O pin in
ECIO and RCIO Oscillator modes.
The other PORTA pins are multiplexed with analog
inputs and the analog V

REF

+ and V

REF

- inputs. The

operation of each pin is selected by clearing/setting the
control bits in the ADCON1 register (A/D Control
Register1).

The TRISA register controls the direction of the RA
pins, even when they are being used as analog inputs.
The user must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.

EXAMPLE 10-1:

INITIALIZING PORTA

WR LAT +

Data Latch

I/O pin

RD Port

WR Port

TRIS

RD LAT

Data Bus

Note:

On a Power-on Reset, RA5 and RA3:RA0
are configured as analog inputs and read
as `0'. RA6 and RA4 are configured as
digital inputs.

CLRF PORTA

;

Initialize PORTA by

; clearing output

; data latches

CLRF LATA

; Alternate method

; to clear output

; data latches

MOVLW 0x0F

; Configure A/D

MOVWF ADCON1

; for digital inputs

MOVLW

0xCF

; Value used to
; initialize data

; direction

MOVWF

TRISA

;

Set RA<3:0> as inputs

;

RA<5:4> as outputs

PIC18FXX20

DS39609A-page 106

Advance Information

2003 Microchip Technology Inc.

10.2

PORTB, TRISB and LATB
Registers

PORTB is an 8-bit wide, bi-directional port. The corre-
sponding Data Direction register is TRISB. Setting a
TRISB bit (= 1) will make the corresponding PORTB
pin an input (i.e., put the corresponding output driver in
a High-Impedance mode). Clearing a TRISB bit (= 0)
will make the corresponding PORTB pin an output (i.e.,
put the contents of the output latch on the selected pin).
The Data Latch register (LATB) is also memory
mapped. Read-modify-write operations on the LATB
register, read and write the latched output value for
PORTB.

EXAMPLE 10-2:

INITIALIZING PORTB

Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is per-
formed by clearing bit RBPU (INTCON2<7>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on a Power-on Reset.

Four of the PORTB pins (RB3:RB0) are the external
interrupt pins, INT3 through INT0. In order to use these
pins as external interrupts, the corresponding TRISB
bit must be set to `1'.
The other four PORTB pins (RB7:RB4) have an inter-
rupt-on-change feature. Only pins configured as inputs
can cause this interrupt to occur (i.e., any RB7:RB4 pin
configured as an output is excluded from the inter-
rupt-on-change comparison). The input pins (of
RB7:RB4) are compared with the old value latched on
the last read of PORTB. The "mismatch" outputs of
RB7:RB4 are OR'ed together to generate the RB Port
Change Interrupt with flag bit, RBIF (INTCON<0>).
This interrupt can wake the device from SLEEP. The
user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
a)

Any read or write of PORTB (except with the
MOVFF

instruction). This will end the mismatch

condition.

Clear flag bit RBIF.

A mismatch condition will continue to set flag bit, RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit RBIF to be cleared.
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
For PIC18F8X20 devices, RB3 can be configured by
the configuration bit CCP2MX, as the alternate periph-
eral pin for the CCP2 module. This is only available
when the device is configured in Microprocessor,
Microprocessor with Boot Block, or Extended
Microcontroller operating modes.
The RB5 pin is used as the LVP programming pin.
When the LVP configuration bit is programmed, this pin
loses the I/O function and become a programming test
function.

FIGURE 10-5:

BLOCK DIAGRAM OF
RB7:RB4 PINS

Note:

On a Power-on Reset, these pins are
configured as digital inputs.

CLRF PORTB

;

Initialize PORTB by

; clearing output

; data latches

CLRF LATB

; Alternate method

; to clear output

; data latches

MOVLW

0xCF

;

Value used to

; initialize data

; direction

MOVWF

TRISB

;

Set RB<3:0> as inputs

;

RB<5:4> as outputs

;

RB<7:6> as inputs

Note: When LVP is enabled, the weak pull-up on

RB5 is disabled.

Data Latch

From other

RBPU

(2)

I/O pin

(1)

Data Bus

WR LATB

WR TRISB

Set RBIF

TRIS Latch

RD TRISB

RD PORTB

RB7:RB4 pins

Weak

Pull-up

RD PORTB

Latch

TTL

Input

Buffer

RB7:RB5 in Serial Programming Mode

RD LATB

or PORTB

Note 1:

I/O pins have diode protection to V

and V

To enable weak pull-ups, set the appropriate TRIS bit(s)
and clear the RBPU bit (INTCON2<7>).

PIC18FXX20

DS39609A-page 108

Advance Information

2003 Microchip Technology Inc.

TABLE 10-3:

PORTB FUNCTIONS

TABLE 10-4:

SUMMARY OF REGISTERS ASSOCIATED WITH PORTB

Name

Bit#

Buffer Function

RB0/INT0

bit0

TTL/ST

(1)

Input/output pin or external interrupt input0.
Internal software programmable weak pull-up.

RB1/INT1

bit1

TTL/ST

(1)

Input/output pin or external interrupt input1.
Internal software programmable weak pull-up.

RB2/INT2

bit2

TTL/ST

(1)

Input/output pin or external interrupt input2.
Internal software programmable weak pull-up.

RB3/CCP2

(3)

/INT3

bit3

TTL/ST

(4)

Input/output pin, or external interrupt input3. Capture2 input/Compare2
output/PWM output (when CCP2MX configuration bit is enabled, all
PIC18F8X20 Operating modes except Microcontroller mode).
Internal software programmable weak pull-up.

RB4/KBI0

bit4

TTL

Input/output pin (with interrupt-on-change).
Internal software programmable weak pull-up.

RB5/KBI1/PGM

bit5

TTL/ST

(2)

Input/output pin (with interrupt-on-change).
Internal software programmable weak pull-up.
Low voltage ICSP enable pin.

RB6/KBI2/PGC

bit6

TTL/ST

(2)

Input/output pin (with interrupt-on-change).
Internal software programmable weak pull-up.
Serial programming clock.

RB7/KBI3/PGD

bit7

TTL/ST

(2)

Input/output pin (with interrupt-on-change).
Internal software programmable weak pull-up.
Serial programming data.

Legend: TTL = TTL input, ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.

2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
3: RC1 is the alternate assignment for CCP2 when CCP2MX is not set (all Operating modes except

Microcontroller mode).

4: This buffer is a Schmitt Trigger input when configured as the CCP2 input.

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR,

BOR

Value on

all other

RESETS

PORTB

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

xxxx xxxx

uuuu uuuu

LATB

LATB Data Output Register

xxxx xxxx

uuuu uuuu

TRISB

PORTB Data Direction Register

1111 1111

INTCON

GIE/

GIEH

PEIE/

GIEL

TMR0IE

INT0IE

RBIE

TMR0IF

INT0IF

RBIF

0000 0000

INTCON2

RBPU

INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP

INT3IP

RBIP

1111 1111

INTCON3

INT2IP

INT1IP

INT3IE

INT2IE

INT1IE

INT3IF

INT2IF

INT1IF

1100 0000

Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB.

2003 Microchip Technology Inc.

Advance Information

DS39609A-page 109

PIC18FXX20

10.3

PORTC, TRISC and LATC
Registers

PORTC is an 8-bit wide, bi-directional port. The corre-
sponding Data Direction register is TRISC. Setting a
TRISC bit (= 1) will make the corresponding PORTC
pin an input (i.e., put the corresponding output driver in
a High-Impedance mode). Clearing a TRISC bit (= 0)
will make the corresponding PORTC pin an output (i.e.,
put the contents of the output latch on the selected pin).
The Data Latch register (LATC) is also memory
mapped. Read-modify-write operations on the LATC
register, read and write the latched output value for
PORTC.
PORTC is multiplexed with several peripheral functions
(Table 10-5). PORTC pins have Schmitt Trigger input
buffers.
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTC pin. Some
peripherals override the TRIS bit to make a pin an out-
put, while other peripherals override the TRIS bit to
make a pin an input. The user should refer to the corre-
sponding peripheral section for the correct TRIS bit
settings.

The pin override value is not loaded into the TRIS reg-
ister. This allows read-modify-write of the TRIS register,
without concern due to peripheral overrides.
RC1 is normally configured by configuration bit,
CCP2MX, as the default peripheral pin of the CCP2
module (default/erased state, CCP2MX = 1).

EXAMPLE 10-3:

INITIALIZING PORTC

FIGURE 10-8:

PORTC BLOCK DIAGRAM (PERIPHERAL OUTPUT OVERRIDE)

Note:

On a Power-on Reset, these pins are
configured as digital inputs.

CLRF PORTC

;

Initialize PORTC by

; clearing output

; data latches

CLRF LATC

; Alternate method

; to clear output

; data latches

MOVLW

0xCF

;

Value used to

; initialize data

; direction

MOVWF

TRISC

;

Set RC<3:0> as inputs

; RC<5:4> as outputs

;

RC<7:6> as inputs

PORTC/Peripheral Out Select

Data Bus

WR LATC

WR TRISC

Data

Latch

TRIS Latch

RD TRISC

Peripheral Data Out

RD PORTC

Peripheral Data In

I/O pin

(1)

WR PORTC

RD LATC

Schmitt

Trigger

Note 1: I/O pins have diode protection to V

and V

2: Peripheral Output Enable is only active if peripheral select is active.

TRIS

Override

Peripheral Output

Logic

TRIS OVERRIDE

Pin

Override

Peripheral

RC0

Yes

Timer1 OSC for

Timer1/Timer3

RC1

Yes

Timer1 OSC for

Timer1/Timer3,

CCP2 I/O

RC2

Yes

CCP1 I/O

RC3

Yes

SPI/I

Master Clock

RC4

Yes

C Data Out

RC5

Yes

SPI Data Out

RC6

Yes

USART1 Async

Xmit, Sync Clock

RC7

Yes

USART1 Sync

Data Out

Enable

(2)

2003 Microchip Technology Inc.

Advance Information

DS39609A-page 111

PIC18FXX20

10.4

PORTD, TRISD and LATD
Registers

PORTD is an 8-bit wide, bi-directional port. The corre-
sponding Data Direction register is TRISD. Setting a
TRISD bit (= 1) will make the corresponding PORTD
pin an input (i.e., put the corresponding output driver in
a High-Impedance mode). Clearing a TRISD bit (= 0)
will make the corresponding PORTD pin an output (i.e.,
put the contents of the output latch on the selected pin).
The Data Latch register (LATD) is also memory
mapped. Read-modify-write operations on the LATD
register, read and write the latched output value for
PORTD.
PORTD is an 8-bit port with Schmitt Trigger input buff-
ers. Each pin is individually configurable as an input or
output.

PORTD is multiplexed with the system bus as the
external memory interface; I/O port functions are only
available when the system bus is disabled, by setting
the EBDIS bit in the MEMCOM register
(MEMCON<7>). When operating as the external mem-
ory interface, PORTD is the low order byte of the
multiplexed address/data bus (AD7:AD0).
PORTD can also be configured as an 8-bit wide micro-
processor port (Parallel Slave Port) by setting control
bit PSPMODE (TRISE<4>). In this mode, the input
buffers are TTL. See Section 10.10 for additional
information on the Parallel Slave Port (PSP).

EXAMPLE 10-4:

INITIALIZING PORTD

FIGURE 10-9:

PORTD BLOCK DIAGRAM
IN I/O PORT MODE

Note:

On a Power-on Reset, these pins are
configured as digital inputs.

CLRF PORTD ; Initialize PORTD by

; clearing output

; data latches

CLRF LATD

; Alternate method

; to clear output

; data latches

MOVLW 0xCF

;

Value used to

; initialize data

; direction

MOVWF TRISD

;

Set RD<3:0> as inputs

;

RD<5:4> as outputs

;

RD<7:6> as inputs

Data
Bus

WR LATD

WR TRISD

RD PORTD

Data Latch

TRIS Latch

RD TRISD

Schmitt
Trigger
Input
Buffer

I/O pin

(1)

RD LATD

or
PORTD

Note 1:

I/O pins have diode protection to V

and V

2003 Microchip Technology Inc.

Advance Information

DS39609A-page 113

PIC18FXX20

TABLE 10-7:

PORTD FUNCTIONS

TABLE 10-8:

SUMMARY OF REGISTERS ASSOCIATED WITH PORTD

Name

Bit#

Buffer Type

Function

RD0/PSP0/AD0

bit0

ST/TTL

(1)

Input/output port pin, parallel slave port bit0 or address/data bus bit0.

RD1/PSP1/AD1

bit1

ST/TTL

(1)

Input/output port pin, parallel slave port bit1 or address/data bus bit1.

RD2/PSP2/AD2

bit2

ST/TTL

(1)

Input/output port pin, parallel slave port bit2 or address/data bus bit2.

RD3/PSP3/AD3

bit3

ST/TTL

(1)

Input/output port pin, parallel slave port bit3 or address/data bus bit3.

RD4/PSP4/AD4

bit4

ST/TTL

(1)

Input/output port pin, parallel slave port bit4 or address/data bus bit4.

RD5/PSP5/AD5

bit5

ST/TTL

(1)

Input/output port pin, parallel slave port bit5 or address/data bus bit5.

RD6/PSP6/AD6

bit6

ST/TTL

(1)

Input/output port pin, parallel slave port bit6 or address/data bus bit6.

RD7/PSP7/AD7

bit7

ST/TTL

(1)

Input/output port pin, parallel slave port bit7 or address/data bus bit7.

Legend: ST = Schmitt Trigger input, TTL = TTL input
Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in System Bus or Parallel Slave

Port mode.

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR, BOR

Value on

all other

RESETS

PORTD

RD7

RD6

RD5

RD4

RD3

RD2

RD1

RD0

xxxx xxxx

uuuu uuuu

LATD

LATD Data Output Register

xxxx xxxx

uuuu uuuu

TRISD

PORTD Data Direction Register

1111 1111

PSPCON

IBF

OBF

IBOV

PSPMODE

0000 ----

MEMCON

EBDIS

WAIT1

WAIT0

WM1

WM0

0-00 --00

Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by PORTD.

PIC18FXX20

DS39609A-page 114

Advance Information

2003 Microchip Technology Inc.

10.5

PORTE, TRISE and LATE
Registers

PORTE is an 8-bit wide, bi-directional port. The corre-
sponding data direction register is TRISE. Setting a
TRISE bit (= 1) will make the corresponding PORTE
pin an input (i.e., put the corresponding output driver in
a High-Impedance mode). Clearing a TRISE bit (= 0)
will make the corresponding PORTE pin an output (i.e.,
put the contents of the output latch on the selected pin).
Read-modify-write operations on the LATE register,
read and write the latched output value for PORTE.
PORTE is an 8-bit port with Schmitt Trigger input buff-
ers. Each pin is individually configurable as an input or
output. PORTE is multiplexed with the CCP module
(Table 10-9).
On PIC18F8X20 devices, PORTE is also multiplexed
with the system bus as the external memory interface;
the I/O bus is available only when the system bus is dis-
abled, by setting the EBDIS bit in the MEMCON regis-
ter (MEMCON<7>). If the device is configured in
Microprocessor or Extended Microcontroller mode,
then the PORTE<7:0> becomes the high byte of the
address/data bus for the external program memory
interface. In Microcontroller mode, the PORTE<2:0>
pins become the control inputs for the Parallel Slave
Port when bit PSPMODE (PSPCON<4>) is set. (Refer
to Section 4.1.1 for more information on Program
Memory modes.)
When the Parallel Slave Port is active, three PORTE
pins (RE0/RD/AD8, RE1/WR/AD9, and RE2/CS/AD10)
function as its control inputs. This automatically occurs
when the PSPMODE bit (PSPCON<4>) is set. Users
must also make certain that bits TRISE<2:0> are set to
configure the pins as digital inputs, and the ADCON1
register is configured for digital I/O. The PORTE PSP
control functions are summarized in Table 10-9.
Pin RE7 can be configured as the alternate peripheral
pin for CCP module 2, when the device is operating in
Microcontroller mode. This is done by clearing the con-
figuration bit CCP2MX in configuration register,
CONFIG3H (CONFIG3H<0>).

EXAMPLE 10-5:

INITIALIZING PORTE

Note:

For PIC18F8X20 (80-pin) devices operat-
ing in Extended Microcontroller mode,
PORTE defaults to the system bus on
Power-on Reset.

CLRF

PORTE

;

Initialize PORTE by

; clearing output

; data latches

CLRF

LATE

; Alternate method

; to clear output

; data latches

MOVLW

0x03

;

Value used to

; initialize data

; direction

MOVWF

TRISE

;

Set RE1:RE0 as inputs

; RE7:RE2 as outputs

PIC18FXX20

DS39609A-page 116

Advance Information

2003 Microchip Technology Inc.

TABLE 10-9:

PORTE FUNCTIONS

TABLE 10-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE

Name

Bit#

Buffer Type

Function

RE0/RD/AD8

bit0

ST/TTL

(1)

Input/output port pin, Read control for parallel slave port, or
address/data bit 8
For RD (PSP Control mode):
1

= Not a read operation

= Read operation, reads PORTD register (if chip selected)

RE1/WR/AD9

bit1

ST/TTL

(1)

Input/output port pin, Write control for parallel slave port, or
address/data bit 9
For WR (PSP Control mode):
1

= Not a write operation

= Write operation, writes PORTD register (if chip selected)

RE2/CS/AD10

bit2

ST/TTL

(1)

Input/output port pin, Chip Select control for parallel slave port, or
address/data bit 10
For CS (PSP Control mode):
1

= Device is not selected

= Device is selected

RE3/AD11

bit3

ST/TTL

(1)

Input/output port pin or address/data bit 11.

RE4/AD12

bit4

ST/TTL

(1)

Input/output port pin or address/data bit 12.

RE5/AD13

bit5

ST/TTL

(1)

Input/output port pin or address/data bit 13.

RE6/AD14

bit6

ST/TTL

(1)

Input/output port pin or address/data bit 14.

RE7/CCP2/AD15

bit7

ST/TTL

(1)

Input/output port pin, Capture2 input/ Compare2 output/PWM output
(PIC18F8X20 devices in Microcontroller mode only), or
address/data bit 15.

Legend: ST = Schmitt Trigger input, TTL = TTL input
Note 1: Input buffers are Schmitt Triggers when in I/O or CCP mode, and TTL buffers when in System Bus or PSP

Control mode.

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on:

POR, BOR

Value on

all other

RESETS

TRISE

PORTE Data Direction Control Register

1111 1111

PORTE

Read PORTE pin/Write PORTE Data Latch

xxxx xxxx

uuuu uuuu

LATE

Read PORTE Data Latch/Write PORTE Data Latch

xxxx xxxx

uuuu uuuu

MEMCON

EBDIS

WAIT1

WAIT0

WM1

WM0

0-00 --00

0000 --00

PSPCON

IBF

OBF

IBOV

PSPMODE

0000 ----

Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTE.

PIC18FXX20

DS39609A-page 120

Advance Information

2003 Microchip Technology Inc.

10.7

PORTG, TRISG and LATG
Registers

PORTG is a 5-bit wide, bi-directional port. The corre-
sponding data direction register is TRISG. Setting a
TRISG bit (= 1) will make the corresponding PORTG
pin an input (i.e., put the corresponding output driver in
a High-Impedance mode). Clearing a TRISG bit (= 0)
will make the corresponding PORTC pin an output (i.e.,
put the contents of the output latch on the selected pin).
The Data Latch register (LATG) is also memory
mapped. Read-modify-write operations on the LATG
register, read and write the latched output value for
PORTG.
PORTG is multiplexed with both CCP and USART
functions (Table 10-13). PORTG pins have Schmitt
Trigger input buffers.
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTG pin. Some
peripherals override the TRIS bit to make a pin an out-
put, while other peripherals override the TRIS bit to

make a pin an input. The user should refer to the corre-
sponding peripheral section for the correct TRIS bit
settings.

The pin override value is not loaded into the TRIS reg-
ister. This allows read-modify-write of the TRIS register,
without concern due to peripheral overrides.

EXAMPLE 10-7:

INITIALIZING PORTG

FIGURE 10-16:

PORTG BLOCK DIAGRAM (PERIPHERAL OUTPUT OVERRIDE)

Note:

On a Power-on Reset, these pins are
configured as digital inputs.

CLRF

PORTG

;

Initialize PORTG by

; clearing output

; data latches

CLRF

LATG

; Alternate method

; to clear output

; data latches

MOVLW

0x04

;

Value used to

; initialize data

; direction

MOVWF

TRISG

;

Set RG1:RG0 as outputs

; RG2 as input

;

RG4:RG3 as inputs

PORTG/Peripheral Out Select

Data Bus

WR LATG

WR TRISG

Data

Latch

TRIS Latch

RD TRISG

Peripheral Data Out

RD PORTG

Peripheral Data In

I/O pin

(1)

WR PORTG

RD LATG

Schmitt

Trigger

Note 1: I/O pins have diode protection to V

and V

2: Peripheral Output Enable is only active if Peripheral Select is active.

TRIS

Override

Peripheral Output

Logic

TRIS OVERRIDE

Pin

Override

Peripheral

RG0

Yes

CCP3 I/O

RG1

Yes

USART1 Async

Xmit, Sync Clock

RG2

Yes

USART1 Async

Rcv, Sync Data

Out

RG3

Yes

CCP4 I/O

RG4

Yes

CCP5 I/O

Enable

(2)

PIC18FXX20

DS39609A-page 122

Advance Information

2003 Microchip Technology Inc.

10.8

PORTH, LATH, and TRISH
Registers

PORTH is an 8-bit wide, bi-directional I/O port. The cor-
responding data direction register is TRISH. Setting a
TRISH bit (= 1) will make the corresponding PORTH
pin an input (i.e., put the corresponding output driver in
a High-Impedance mode). Clearing a TRISH bit (= 0)
will make the corresponding PORTH pin an output (i.e.,
put the contents of the output latch on the selected pin).
Read-modify-write operations on the LATH register,
read and write the latched output value for PORTH.
Pins RH7:RH4 are multiplexed with analog inputs
AN15:AN12. Pins RH3:RH0 are multiplexed with the
system bus as the external memory interface; they are
the high order address bits, A19:A16. By default, pins
RH7:RH4 are enabled as A/D inputs and pins
RH3:RH0 are enabled as the system address bus.
Register ADCON1 configures RH7:RH4 as I/O or A/D
inputs. Register MEMCON configures RH3:RH0 as I/O
or system bus pins.

EXAMPLE 10-8:

INITIALIZING PORTH

FIGURE 10-17:

RH3:RH0 PINS BLOCK
DIAGRAM IN I/O MODE

FIGURE 10-18:

RH7:RH4 PINS BLOCK
DIAGRAM IN I/O MODE

Note:

PORTH is available only on PIC18F8X20
devices.

Note 1: On Power-on Reset, PORTH pins

RH7:RH4 default to A/D inputs and read
as `0'.

2: On Power-on Reset, PORTH pins

RH3:RH0 default to system bus signals.

CLRF PORTH ; Initialize PORTH by

; clearing output

; data latches

CLRF LATH ; Alternate method

; to clear output

; data latches

MOVLW 0Fh ;

MOVWF ADCON1 ;

MOVLW 0CFh ; Value used to

; initialize data

; direction

MOVWF TRISH ; Set RH3:RH0 as inputs

; RH5:RH4 as outputs

; RH7:RH6 as inputs

Data

Bus

WR LATH

WR TRISH

RD PORTH

Data Latch

TRIS Latch

RD TRISH

Schmitt

Trigger

Input

Buffer

I/O pin

(1)

RD LATH

PORTH

Note 1: I/O pins have diode protection to V

and V

Data

Bus

WR LATH

WR TRISH

RD PORTH

Data Latch

TRIS Latch

RD TRISH

Schmitt

Trigger

Input

Buffer

I/O pin

(1)

RD LATH

PORTH

To A/D Converter

Note 1: I/O pins have diode protection to V

and V

2003 Microchip Technology Inc.

Advance Information

DS39609A-page 125

PIC18FXX20

10.9

PORTJ, TRISJ and LATJ
Registers

PORTJ is an 8-bit wide, bi-directional port. The corre-
sponding Data Direction register is TRISJ. Setting a
TRISJ bit (= 1) will make the corresponding PORTJ pin
an input (i.e., put the corresponding output driver in a
High-Impedance mode). Clearing a TRISJ bit (= 0) will
make the corresponding PORTJ pin an output (i.e., put
the contents of the output latch on the selected pin).
The Data Latch register (LATJ) is also memory
mapped. Read-modify-write operations on the LATJ
register, read and write the latched output value for
PORTJ.
PORTJ is multiplexed with the system bus as the exter-
nal memory interface; I/O port functions are only avail-
able when the system bus is disabled. When operating
as the external memory interface, PORTJ provides the
control signal to external memory devices. The RJ5 pin
is not multiplexed with any system bus functions.
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTJ pin. Some
peripherals override the TRIS bit to make a pin an out-
put, while other peripherals override the TRIS bit to
make a pin an input. The user should refer to the corre-
sponding peripheral section for the correct TRIS bit
settings.

The pin override value is not loaded into the TRIS reg-
ister. This allows read-modify-write of the TRIS register,
without concern due to peripheral overrides.

EXAMPLE 10-9:

INITIALIZING PORTJ

FIGURE 10-20:

PORTJ BLOCK DIAGRAM
IN I/O MODE

Note:

PORTJ is available only on PIC18F8X20
devices.

Note:

On a Power-on Reset, these pins are
configured as digital inputs.

CLRF PORTJ

;

Initialize PORTG by

; clearing output

; data latches

CLRF LATJ

; Alternate method

; to clear output

; data latches

MOVLW

0xCF

;

Value used to

; initialize data

; direction

MOVWF

TRISJ

;

Set RJ3:RJ0 as inputs

; RJ5:RJ4 as output

;

RJ7:RJ6 as inputs

Data

Bus

WR LATJ

WR TRISJ

RD PORTJ

Data Latch

TRIS Latch

RD TRISJ

Schmitt

Trigger

Input

Buffer

I/O pin

(1)

RD LATJ

PORTJ

Note 1: I/O pins have diode protection to V

and V

PIC18FXX20

DS39609A-page 128

Advance Information

2003 Microchip Technology Inc.

10.10 Parallel Slave Port

PORTD also operates as an 8-bit wide Parallel Slave
Port, or microprocessor port, when control bit
PSPMODE (PSPCON<4>) is set. It is asynchronously
readable and writable by the external world through RD
control input pin, RE0/RD/AD8 and WR control input
pin, RE1/WR/AD9.

The PSP can directly interface to an 8-bit micro-
processor data bus. The external microprocessor can
read or write the PORTD latch as an 8-bit latch. Setting
bit PSPMODE enables port pin RE0/RD/AD8 to be the
RD input, RE1/WR/AD9 to be the WR input and
RE2/CS/AD10 to be the CS (chip select) input. For this
functionality, the corresponding data direction bits of
the TRISE register (TRISE<2:0>) must be configured
as inputs (set). The A/D port configuration bits
PCFG2:PCFG0 (ADCON1<2:0>) must be set, which
will configure pins RE2:RE0 as digital I/O.
A write to the PSP occurs when both the CS and WR
lines are first detected low. A read from the PSP occurs
when both the CS and RD lines are first detected low.
The PORTE I/O pins become control inputs for the
microprocessor port when bit PSPMODE
(PSPCON<4>) is set. In this mode, the user must make
sure that the TRISE<2:0> bits are set (pins are config-
ured as digital inputs), and the ADCON1 is configured
for digital I/O. In this mode, the input buffers are TTL.

FIGURE 10-23:

PORTD AND PORTE
BLOCK DIAGRAM
(PARALLEL SLAVE
PORT)

Note:

For PIC18F8X20 devices, the Parallel
Slave Port is available only in
Microcontroller mode.

Data Bus

WR LATD

RDx

RD PORTD

One bit of PORTD

Set Interrupt Flag

PSPIF (PIR1<7>)

Read

Chip Select

Write

Note: I/O pin has protection diodes to V

and V

TTL

PORTD

RD LATD

Data Latch

TRIS Latch

2003 Microchip Technology Inc.

Advance Information

DS39609A-page 131

PIC18FXX20

11.0 TIMER0 MODULE

The Timer0 module has the following features:
� Software selectable as an 8-bit or 16-bit

timer/counter

� Readable and writable
� Dedicated 8-bit software programmable prescaler
� Clock source selectable to be external or internal
� Interrupt-on-overflow from FFh to 00h in 8-bit

mode and FFFFh to 0000h in 16-bit mode

� Edge select for external clock

Figure 11-1 shows a simplified block diagram of the
Timer0 module in 8-bit mode and Figure 11-2 shows a
simplified block diagram of the Timer0 module in 16-bit
mode.
The T0CON register (Register 11-1) is a readable and
writable register that controls all the aspects of Timer0,
including the prescale selection.

REGISTER 11-1:

T0CON: TIMER0 CONTROL REGISTER

R/W-1

TMR0ON

T08BIT

T0CS

T0SE

PSA

T0PS2

T0PS1

T0PS0

bit 7

bit 0

bit 7

TMR0ON: Timer0 On/Off Control bit

= Enables Timer0

= Stops Timer0

bit 6

T08BIT: Timer0 8-bit/16-bit Control bit

= Timer0 is configured as an 8-bit timer/counter

= Timer0 is configured as a 16-bit timer/counter

bit 5

T0CS: Timer0 Clock Source Select bit

= Transition on T0CKI pin

= Internal instruction cycle clock (CLKO)

bit 4

T0SE: Timer0 Source Edge Select bit

= Increment on high-to-low transition on T0CKI pin

= Increment on low-to-high transition on T0CKI pin

bit 3

PSA: Timer0 Prescaler Assignment bit

= TImer0 prescaler is NOT assigned. Timer0 clock input bypasses prescaler.

= Timer0 prescaler is assigned. Timer0 clock input comes from prescaler output.

bit 2-0

T0PS2:T0PS0: Timer0 Prescaler Select bits

111

= 1:256 prescale value

110

= 1:128 prescale value

101

= 1:64 prescale value

100

= 1:32 prescale value

011

= 1:16 prescale value

010

= 1:8 prescale value

001

= 1:4 prescale value

000

= 1:2 prescale value

Legend:
R = Readable bit

W = Writable bit

U = Unimplemented bit, read as `0'

- n = Value at POR

`1' = Bit is set

`0' = Bit is cleared

x = Bit is unknown

2003 Microchip Technology Inc.

Advance Information

DS39609A-page 133

PIC18FXX20

11.1

Timer0 Operation

Timer0 can operate as a timer or as a counter.
Timer mode is selected by clearing the T0CS bit. In
Timer mode, the Timer0 module will increment every
instruction cycle (without prescaler). If the TMR0 regis-
ter is written, the increment is inhibited for the following
two instruction cycles. The user can work around this
by writing an adjusted value to the TMR0 register.
Counter mode is selected by setting the T0CS bit. In
Counter mode, Timer0 will increment, either on every
rising or falling edge of pin RA4/T0CKI. The increment-
ing edge is determined by the Timer0 Source Edge
Select bit (T0SE). Clearing the T0SE bit selects the ris-
ing edge. Restrictions on the external clock input are
discussed below.
When an external clock input is used for Timer0, it must
meet certain requirements. The requirements ensure
the external clock can be synchronized with the internal
phase clock (T

OSC

). Also, there is a delay in the actual

incrementing of Timer0 after synchronization.

11.2

Prescaler

An 8-bit counter is available as a prescaler for the Timer0
module. The prescaler is not readable or writable.
The PSA and T0PS2:T0PS0 bits determine the
prescaler assignment and prescale ratio.
Clearing bit PSA will assign the prescaler to the Timer0
module. When the prescaler is assigned to the Timer0
module, prescale values of 1:2, 1:4,..., 1:256 are
selectable.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g., CLRF TMR0, MOVWF
TMR0, BSF TMR0, x

....etc.) will clear the prescaler

count.

11.2.1

SWITCHING PRESCALER
ASSIGNMENT

The prescaler assignment is fully under software con-
trol, (i.e., it can be changed "on-the-fly" during program
execution).

11.3

Timer0 Interrupt

The TMR0 interrupt is generated when the TMR0 reg-
ister overflows from FFh to 00h in 8-bit mode, or FFFFh
to 0000h in 16-bit mode. This overflow sets the TMR0IF
bit. The interrupt can be masked by clearing the
TMR0IE bit. The TMR0IE bit must be cleared in soft-
ware by the Timer0 module Interrupt Service Routine,
before re-enabling this interrupt. The TMR0 interrupt
cannot awaken the processor from SLEEP, since the
timer is shut-off during SLEEP.

11.4

16-Bit Mode Timer Reads and
Writes

TMR0H is not the high byte of the timer/counter in
16-bit mode, but is actually a buffered version of the
high byte of Timer0 (refer to Figure 11-2). The high byte
of the Timer0 counter/timer is not directly readable nor
writable. TMR0H is updated with the contents of the
high byte of Timer0 during a read of TMR0L. This pro-
vides the ability to read all 16 bits of Timer0 without
having to verify that the read of the high and low byte
were valid, due to a rollover between successive reads
of the high and low byte.
A write to the high byte of Timer0 must also take place
through the TMR0H buffer register. Timer0 high byte is
updated with the contents of TMR0H when a write
occurs to TMR0L. This allows all 16 bits of Timer0 to be
updated at once.

TABLE 11-1:

REGISTERS ASSOCIATED WITH TIMER0

Note:

Writing to TMR0 when the prescaler is
assigned to Timer0, will clear the prescaler
count, but will not change the prescaler
assignment.

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR, BOR

Value on

all other

RESETS

TMR0L

Timer0 Module Low Byte Register

xxxx xxxx uuuu uuuu

TMR0H

Timer0 Module High Byte Register

0000 0000 0000 0000

INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE

RBIE TMR0IF INT0IF

RBIF

0000 0000 0000 0000

T0CON

TMR0ON

T08BIT

T0CS

T0SE

PSA

T0PS2 T0PS1 T0PS0 1111 1111 1111 1111

TRISA

PORTA Data Direction Register

-111 1111 -111 1111

Legend: x = unknown, u = unchanged, - = unimplemented locations, read as '0'. Shaded cells are not used by Timer0.

2003 Microchip Technology Inc.

Advance Information

DS39609A-page 135

PIC18FXX20

12.0 TIMER1 MODULE

The Timer1 module timer/counter has the following
features:
� 16-bit timer/counter

(two 8-bit registers: TMR1H and TMR1L)

� Readable and writable (both registers)
� Internal or external clock select
� Interrupt-on-overflow from FFFFh to 0000h
� RESET from CCP module special event trigger
Figure 12-1 is a simplified block diagram of the Timer1
module.

Register 12-1 details the Timer1 control register. This
register controls the Operating mode of the Timer1
module, and contains the Timer1 oscillator enable bit
(T1OSCEN). Timer1 can be enabled or disabled by
setting or clearing control bit, TMR1ON (T1CON<0>).
Timer1 can also be used to provide Real-Time Clock
(RTC) functionality to applications, with only a minimal
addition of external components and code overhead.

REGISTER 12-1:

T1CON: TIMER1 CONTROL REGISTER

R/W-0

U-0

R/W-0

RD16

T1CKPS1

T1CKPS0

T1OSCEN

T1SYNC

TMR1CS

TMR1ON

bit 7

bit 0

bit 7

RD16: 16-bit Read/Write Mode Enable bit

= Enables register Read/Write of Timer1 in one 16-bit operation

= Enables register Read/Write of Timer1 in two 8-bit operations

bit 6

Unimplemented: Read as '0'

bit 5-4

T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits

= 1:8 Prescale value

= 1:4 Prescale value

= 1:2 Prescale value

= 1:1 Prescale value

bit 3

T1OSCEN: Timer1 Oscillator Enable bit

= Timer1 Oscillator is enabled

= Timer1 Oscillator is shut-off

The oscillator inverter and feedback resistor are turned off to eliminate power drain.

bit 2

T1SYNC: Timer1 External Clock Input Synchronization Select bit
When TMR1CS = 1:
1

= Do not synchronize external clock input

= Synchronize external clock input

When TMR1CS = 0:
This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.

bit 1

TMR1CS: Timer1 Clock Source Select bit

= External clock from pin RC0/T1OSO/T13CKI (on the rising edge)

= Internal clock (F

OSC

/4)

bit 0

TMR1ON: Timer1 On bit

= Enables Timer1

= Stops Timer1

Legend:
R = Readable bit

W = Writable bit

U = Unimplemented bit, read as `0'

- n = Value at POR

`1' = Bit is set

`0' = Bit is cleared

x = Bit is unknown

PIC18FXX20

DS39609A-page 136

Advance Information

2003 Microchip Technology Inc.

12.1

Timer1 Operation

Timer1 can operate in one of these modes:
� As a timer
� As a synchronous counter
� As an asynchronous counter
The Operating mode is determined by the clock select
bit, TMR1CS (T1CON<1>).

When TMR1CS = 0, Timer1 increments every instruc-
tion cycle. When TMR1CS = 1, Timer1 increments on
every rising edge of the external clock input, or the
Timer1 oscillator, if enabled.
When the Timer1 oscillator is enabled (T1OSCEN is
set), the RC1/T1OSI and RC0/T1OSO/T13CKI pins
become inputs. That is, the TRISC<1:0> value is
ignored, and the pins are read as `0'.
Timer1 also has an internal "RESET input". This
RESET can be generated by the CCP module
(Section 16.0).

FIGURE 12-1:

TIMER1 BLOCK DIAGRAM

FIGURE 12-2:

TIMER1 BLOCK DIAGRAM: 16-BIT READ/WRITE MODE

TMR1H

TMR1L

T1SYNC

TMR1CS

T1CKPS1:T1CKPS0

SLEEP Input

OSC

Internal

Clock

TMR1ON

On/Off

Prescaler

1, 2, 4, 8

Synchronize

det

Synchronized

Clock Input

TMR1IF
Overflow

TMR1

CLR

CCP Special Event Trigger

T1OSCEN
Enable
Oscillator

(1)

T1OSC

Interrupt
Flag Bit

Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.

T1OSI

T13CKI/T1OSO

Timer 1

TMR1L

T1OSC

T1SYNC

TMR1CS

T1CKPS1:T1CKPS0

SLEEP Input

T1OSCEN

Enable

Oscillator

(1)

TMR1IF

Overflow

Interrupt

OSC

Internal

Clock

TMR1ON

On/Off

Prescaler

1, 2, 4, 8

Synchronize

det

Synchronized

Clock Input

T13CKI/T1OSO

T1OSI

TMR1

Flag bit

Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.

High Byte

Data Bus<7:0>

TMR1H

Read TMR1L

Write TMR1L

CLR

CCP Special Event Trigger

2003 Microchip Technology Inc.

Advance Information

DS39609A-page 137

PIC18FXX20

12.2

Timer1 Oscillator

A crystal oscillator circuit is built-in between pins T1OSI
(input) and T1OSO (amplifier output). It is enabled by
setting control bit, T1OSCEN (T1CON<3>). The oscil-
lator is a low power oscillator rated up to 200 kHz. It will
continue to run during SLEEP. It is primarily intended
for a 32 kHz crystal. The circuit for a typical LP oscilla-
tor is shown in Figure 12-3. Table 12-1 shows the
capacitor selection for the Timer1 oscillator.
The user must provide a software time delay to ensure
proper start-up of the Timer1 oscillator

FIGURE 12-3:

EXTERNAL
COMPONENTS FOR THE
TIMER1 LP OSCILLATOR

12.2.1

LOW POWER TIMER1 OPTION
(PIC18FX520 DEVICES ONLY)

The Timer1 oscillator for PIC18FX520 devices incorpo-
rates an additional low power feature. When this option
is selected, it allows the oscillator to automatically
reduce its power consumption when the microcontroller
is in SLEEP mode. During normal device operation, the
oscillator draws full current. As high noise environ-
ments may cause excessive oscillator instability in
SLEEP mode, this option is best suited for low noise
applications where power conservation is an important
design consideration.
The low power option is enabled by clearing the
T1OSCMX bit (CONFIG3H<1>). By default, the option
is disabled, which results in a more-or-less constant
current draw for the Timer1 oscillator.
Due to the low power nature of the oscillator, it may also
be sensitive to rapidly changing signals in close
proximity.
The oscillator circuit, shown in Figure 12-3, should be
located as close as possible to the microcontroller.
There should be no circuits passing within the oscillator
circuit boundaries other than V

or V

If a high speed circuit must be located near the oscilla-
tor (such as the CCP1 pin in output compare or PWM
mode, or the primary oscillator using the OSC2 pin), a
grounded guard ring around the oscillator circuit, as
shown in Figure 12-4, may be helpful when used on a
single sided PCB, or in addition to a ground plane.

FIGURE 12-4:

OSCILLATOR CIRCUIT
WITH GROUNDED
GUARD RING

TABLE 12-1:

CAPACITOR SELECTION FOR
THE ALTERNATE
OSCILLATOR

Osc Type

Freq

32 kHz

TBD

(1)

TBD

(1)

Crystal to be Tested:

32.768 kHz Epson C-001R32.768K-A

� 20 PPM

Note 1: Microchip suggests 33 pF as a starting

point in validating the oscillator circuit.

2: Higher capacitance increases the stability

of the oscillator, but also increases the
start-up time.

3: Since each resonator/crystal has its own

characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate values of external
components.

4: Capacitor values are for design guidance

only.

Note:

See the Notes with Table 12-1 for additional
information about capacitor selection.

XTAL

PIC18FXX20

T1OSI

T1OSO

32.768 kHz

33 pF

OSC1

OSC2

RC0

RC1

RC2

Note: Not drawn to scale.

PIC18FXX20

DS39609A-page 138

Advance Information

2003 Microchip Technology Inc.

12.3

Timer1 Interrupt

The TMR1 Register pair (TMR1H:TMR1L) increments
from 0000h to FFFFh and rolls over to 0000h. The
TMR1 interrupt, if enabled, is generated on overflow,
which is latched in interrupt flag bit, TMR1IF
(PIR1<0>). This interrupt can be enabled/disabled by
setting/clearing TMR1 interrupt enable bit, TMR1IE
(PIE1<0>).

12.4

Resetting Timer1 using a CCP
Trigger Output

If the CCP module is configured in Compare mode
to generate a "special event trigger"
(CCP1M3:CCP1M0 = 1011), this signal will reset
Timer1 and start an A/D conversion (if the A/D module
is enabled).

Timer1 must be configured for either Timer or Synchro-
nized Counter mode to take advantage of this feature.
If Timer1 is running in Asynchronous Counter mode,
this RESET operation may not work.
In the event that a write to Timer1 coincides with a
special event trigger from CCP1, the write will take
precedence.
In this mode of operation, the CCPR1H:CCPR1L regis-
ters pair effectively becomes the period register for
Timer1.

12.5

Timer1 16-Bit Read/Write Mode

Timer1 can be configured for 16-bit reads and writes
(see Figure 12-2). When the RD16 control bit
(T1CON<7>) is set, the address for TMR1H is mapped
to a buffer register for the high byte of Timer1. A read
from TMR1L will load the contents of the high byte of
Timer1 into the Timer1 high byte buffer. This provides
the user with the ability to accurately read all 16-bits of
Timer1 without having to determine whether a read of
the high byte, followed by a read of the low byte, is
valid, due to a rollover between reads.
A write to the high byte of Timer1 must also take place
through the TMR1H buffer register. Timer1 high byte is
updated with the contents of TMR1H when a write
occurs to TMR1L. This allows a user to write all 16 bits
to both the high and low bytes of Timer1 at once.
The high byte of Timer1 is not directly readable or writ-
able in this mode. All reads and writes must take place
through the Timer1 high byte buffer register. Writes to
TMR1H do not clear the Timer1 prescaler. The
prescaler is only cleared on writes to TMR1L.

12.6

Using Timer1 as a Real-Time
Clock

Adding an external LP oscillator to Timer1 (such as the
one described in Section 12.2, above) gives users the
option to include RTC functionality to their applications.
This is accomplished with an inexpensive watch crystal
to provide an accurate time-base, and several lines of
application code to calculate the time. When operating
in SLEEP mode and using a battery or supercapacitor
as a power source, it can completely eliminate the need
for a separate RTC device and battery backup.
The application code routine, RTCisr, shown in
Example 12-1, demonstrates a simple method to incre-
ment a counter at one-second intervals using an Inter-
rupt Service Routine. Incrementing the TMR1 register
pair to overflow, triggers the interrupt and calls the rou-
tine, which increments the seconds counter by one;
additional counters for minutes and hours are
incremented as the previous counter overflow.
Since the register pair is 16-bits wide, counting up to
overflow the register directly from a 32.768 kHz clock
would take 2 seconds. To force the overflow at the
required one-second intervals, it is necessary to pre-
load it; the simplest method is to set the MSbit of
TMR1H with a BSF instruction. Note that the TMR1L
register is never pre-loaded or altered; doing so may
introduce cumulative error over many cycles.
For this method to be accurate, Timer1 must operate in
Asynchronous mode, and the Timer1 Overflow inter-
rupt must be enabled (PIE1<0> = 1), as shown in the
routine, RTCinit. The Timer1 oscillator must also be
enabled and running at all times.

Note:

The special event triggers from the CCP1
module will not set interrupt flag bit
TMR1IF (PIR1<0>).

2003 Microchip Technology Inc.

Advance Information

DS39609A-page 139

PIC18FXX20

EXAMPLE 12-1:

IMPLEMENTING A REAL-TIME CLOCK USING A TIMER1 INTERRUPT SERVICE

TABLE 12-2:

REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER

RTCinit

movlw

0x80

; Preload TMR1 register pair

movwf

TMR1H

; for 1 second overflow

clrf

TMR1L

movlw

b'00001111'

; Configure for external clock,

movwf

T1OSC

; Asynchronous operation, external oscillator

clrf

secs

; Initialize timekeeping registers

clrf

mins

;

movlw

.12

movwf

hours

bsf

PIE1, TMR1IE

; Enable Timer1 interrupt

return

RTCisr

bsf

TMR1H,7

; Preload for 1 sec overflow

bcf

PIR1,TMR1IF

; Clear interrupt flag

incf

secs,F

; Increment seconds

movlw

.59

; 60 seconds elapsed?

cpfsgt secs
return

; No, done

clrf

secs

; Clear seconds

incf

mins,F

; Increment minutes

movlw

.59

; 60 minutes elapsed?

cpfsgt mins
return

; No, done

clrf

mins

; clear minutes

incf

hours,F

; Increment hours

movlw

.23

; 24 hours elapsed?

cpfsgt hours
return

; No, done

movlw

.01

; Reset hours to 1

movwf

hours

return

; Done

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR, BOR

Value on
all other

RESETS

INTCON

GIE/GIEH PEIE/GIEL TMR0IE

INT0IE

RBIE

TMR0IF

INT0IF

RBIF

0000 0000 0000 0000

PIR1

PSPIF

ADIF

RCIF

TXIF

SSPIF

CCP1IF

TMR2IF

TMR1IF 0000 0000 0000 0000

PIE1

PSPIE

ADIE

RCIE

TXIE

SSPIE

CCP1IE

TMR2IE

TMR1IE 0000 0000 0000 0000

IPR1

PSPIP

ADIP

RCIP

TXIP

SSPIP

CCP1IP

TMR2IP

TMR1IP 0111 1111 0111 1111

TMR1L

Holding Register for the Least Significant Byte of the 16-bit TMR1 Register

xxxx xxxx uuuu uuuu

TMR1H

Holding Register for the Most Significant Byte of the 16-bit TMR1 Register

xxxx xxxx uuuu uuuu

T1CON

RD16

T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 u-uu uuuu

Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Timer1 module.

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PIC18FXX20

13.0 TIMER2 MODULE

The Timer2 module timer has the following features:
� 8-bit timer (TMR2 register)
� 8-bit period register (PR2)
� Readable and writable (both registers)
� Software programmable prescaler (1:1, 1:4, 1:16)
� Software programmable postscaler (1:1 to 1:16)
� Interrupt on TMR2 match of PR2
� SSP module optional use of TMR2 output to

generate clock shift

Timer2 has a control register shown in Register 13-1.
Timer2 can be shut-off by clearing control bit, TMR2ON
(T2CON<2>), to minimize power consumption.
Figure 13-1 is a simplified block diagram of the Timer2
module. Register 13-1 shows the Timer2 control regis-
ter. The prescaler and postscaler selection of Timer2
are controlled by this register.

13.1

Timer2 Operation

Timer2 can be used as the PWM time-base for the
PWM mode of the CCP module. The TMR2 register is
readable and writable, and is cleared on any device
RESET. The input clock (F

OSC

/4) has a prescale option

of 1:1, 1:4 or 1:16, selected by control bits,
T2CKPS1:T2CKPS0 (T2CON<1:0>). The match out-
put of TMR2 goes through a 4-bit postscaler (which
gives a 1:1 to 1:16 scaling inclusive) to generate a
TMR2 interrupt (latched in flag bit, TMR2IF (PIR1<1>)).
The prescaler and postscaler counters are cleared
when any of the following occurs:
� a write to the TMR2 register
� a write to the T2CON register
� any device RESET (Power-on Reset, MCLR

Reset, Watchdog Timer Reset, or Brown-out
Reset)

TMR2 is not cleared when T2CON is written.

REGISTER 13-1:

T2CON: TIMER2 CONTROL REGISTER

U-0

R/W-0

T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0

bit 7

bit 0

bit 7

Unimplemented: Read as '0'

bit 6-3

T2OUTPS3:T2OUTPS0: Timer2 Output Postscale Select bits

0000

= 1:1 Postscale

0001

= 1:2 Postscale

�
�
�
1111

= 1:16 Postscale

bit 2

TMR2ON: Timer2 On bit

= Timer2 is on

= Timer2 is off

bit 1-0

T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits

= Prescaler is 1

= Prescaler is 4

= Prescaler is 16

Legend:
R = Readable bit

W = Writable bit

U = Unimplemented bit, read as `0'

- n = Value at POR

`1' = Bit is set

`0' = Bit is cleared

x = Bit is unknown

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PIC18FXX20

14.0 TIMER3 MODULE

The Timer3 module timer/counter has the following
features:
� 16-bit timer/counter

(two 8-bit registers; TMR3H and TMR3L)

� Readable and writable (both registers)
� Internal or external clock select
� Interrupt-on-overflow from FFFFh to 0000h
� RESET from CCP module trigger

Figure 14-1 is a simplified block diagram of the Timer3
module.
Register 14-1 shows the Timer3 control register. This
register controls the Operating mode of the Timer3
module and sets the CCP clock source.
Register 12-1 shows the Timer1 control register. This
register controls the Operating mode of the Timer1
module, as well as contains the Timer1 oscillator
enable bit (T1OSCEN), which can be a clock source for
Timer3.

REGISTER 14-1:

T3CON: TIMER3 CONTROL REGISTER

R/W-0

RD16

T3CCP2 T3CKPS1 T3CKPS0

T3CCP1

T3SYNC

TMR3CS

TMR3ON

bit 7

bit 0

bit 7

RD16: 16-bit Read/Write Mode Enable bit

= Enables register Read/Write of Timer3 in one 16-bit operation

= Enables register Read/Write of Timer3 in two 8-bit operations

bit 6,3

T3CCP2:T3CCP1: Timer3 and Timer1 to CCPx Enable bits

= Timer3 and Timer4 are the clock sources for CCP1 through CCP5

= Timer3 and Timer4 are the clock sources for CCP3 through CCP5;

Timer1 and Timer2 are the clock sources for CCP1 and CCP2

= Timer3 and Timer4 are the clock sources for CCP2 through CCP5;

Timer1 and Timer2 are the clock sources for CCP1

= Timer1 and Timer2 are the clock sources for CCP1 through CCP5

bit 5-4

T3CKPS1:T3CKPS0: Timer3 Input Clock Prescale Select bits

= 1:8 Prescale value

= 1:4 Prescale value

= 1:2 Prescale value

= 1:1 Prescale value

bit 2

T3SYNC: Timer3 External Clock Input Synchronization Control bit
(Not usable if the system clock comes from Timer1/Timer3.)
When TMR3CS = 1:
1

= Do not synchronize external clock input

= Synchronize external clock input

When TMR3CS = 0:
This bit is ignored. Timer3 uses the internal clock when TMR3CS = 0.

bit 1

TMR3CS: Timer3 Clock Source Select bit

= External clock input from Timer1 oscillator or T13CKI

(on the rising edge after the first falling edge)

= Internal clock (F

OSC

/4)

bit 0

TMR3ON: Timer3 On bit

= Enables Timer3

= Stops Timer3

Legend:
R = Readable bit

W = Writable bit

U = Unimplemented bit, read as `0'

- n = Value at POR

`1' = Bit is set

`0' = Bit is cleared

x = Bit is unknown

PIC18FXX20

DS39609A-page 144

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2003 Microchip Technology Inc.

14.1

Timer3 Operation

Timer3 can operate in one of these modes:
� As a timer
� As a synchronous counter
� As an asynchronous counter
The Operating mode is determined by the clock select
bit, TMR3CS (T3CON<1>).

When TMR3CS = 0, Timer3 increments every instruc-
tion cycle. When TMR3CS = 1, Timer3 increments on
every rising edge of the Timer1 external clock input or
the Timer1 oscillator, if enabled.
When the Timer1 oscillator is enabled (T1OSCEN is
set), the RC1/T1OSI and RC0/T1OSO/T13CKI pins
become inputs. That is, the TRISC<1:0> value is
ignored, and the pins are read as `0'.
Timer3 also has an internal "RESET input". This RESET
can be generated by the CCP module (Section 14.0).

FIGURE 14-1:

TIMER3 BLOCK DIAGRAM

FIGURE 14-2:

TIMER3 BLOCK DIAGRAM CONFIGURED IN 16-BIT READ/WRITE MODE

TMR3H

TMR3L

T1OSC

T3SYNC

TMR3CS

T3CKPS1:T3CKPS0

SLEEP Input

T1OSCEN

Enable

Oscillator

(1)

TMR3IF

Overflow

Interrupt

OSC

Internal

Clock

TMR3ON

On/Off

Prescaler

1, 2, 4, 8

Synchronize

det

Synchronized

Clock Input

T1OSO/

T1OSI

Flag bit

(3)

Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.

T13CKI

CLR

CCP Special Trigger

T3CCPx

Timer3

TMR3L

T1OSC

T3SYNC

TMR3CS

T3CKPS1:T3CKPS0

SLEEP Input

T1OSCEN

Enable

Oscillator

(1)

OSC

Internal

Clock

TMR3ON

On/Off

Prescaler

1, 2, 4, 8

Synchronize

det

Synchronized

Clock Input

T1OSO/

T1OSI

TMR3

T13CKI

CLR

CCP Special Trigger

T3CCPx

To Timer1 Clock Input

Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.

High Byte

Data Bus<7:0>

TMR3H

Read TMR3L

Write TMR3L

Set TMR3IF Flag bit
on Overflow

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PIC18FXX20

14.2

Timer1 Oscillator

The Timer1 oscillator may be used as the clock source
for Timer3. The Timer1 oscillator is enabled by setting
the T1OSCEN (T1CON<3>) bit. The oscillator is a low
power oscillator rated up to 200 kHz. See Section 12.0
for further details.

14.3

Timer3 Interrupt

The TMR3 register pair (TMR3H:TMR3L) increments
from 0000h to FFFFh and rolls over to 0000h. The
TMR3 interrupt, if enabled, is generated on overflow,
which is latched in interrupt flag bit, TMR3IF
(PIR2<1>). This interrupt can be enabled/disabled by
setting/clearing TMR3 interrupt enable bit, TMR3IE
(PIE2<1>).

14.4

Resetting Timer3 Using a CCP
Trigger Output

If the CCP module is configured in Compare mode
to generate a "special event trigger"
(CCP1M3:CCP1M0 = 1011), this signal will reset
Timer3.

Timer3 must be configured for either Timer or Synchro-
nized Counter mode to take advantage of this feature.
If Timer3 is running in Asynchronous Counter mode,
this RESET operation may not work. In the event that a
write to Timer3 coincides with a special event trigger
from CCP1, the write will take precedence. In this mode
of operation, the CCPR1H:CCPR1L registers pair
effectively becomes the period register for Timer3.

TABLE 14-1:

REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER

Note:

The special event triggers from the CCP
module will not set interrupt flag bit,
TMR3IF (PIR1<0>).

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR, BOR

Value on

all other

RESETS

INTCON

GIE/

GIEH

PEIE/

GIEL

TMR0IE

INT0IE

RBIE

TMR0IF

INT0IF

RBIF

0000 0000

PIR2

EEIF

BCLIF

LVDIF

TMR3IF

CCP2IF

---0 0000

PIE2

EEIE

BCLIE

LVDIE

TMR3IE

CCP2IE

---0 0000

IPR2

EEIP

BCLIP

LVDIP

TMR3IP

CCP2IP

---1 1111

TMR3L

Holding Register for the Least Significant Byte of the 16-bit TMR3 Register

xxxx xxxx

uuuu uuuu

TMR3H

Holding Register for the Most Significant Byte of the 16-bit TMR3 Register

xxxx xxxx

uuuu uuuu

T1CON

RD16

T1CKPS1 T1CKPS0 T1OSCEN T1SYNC

TMR1CS TMR1ON 0-00 0000 u-uu uuuu

T3CON

RD16

T3CCP2

T3CKPS1 T3CKPS0

T3CCP1

T3SYNC

TMR3CS TMR3ON 0000 0000 uuuu uuuu

Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Timer3 module.

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PIC18FXX20

15.0 TIMER4 MODULE

The Timer4 module timer has the following features:
� 8-bit timer (TMR4 register)
� 8-bit period register (PR4)
� Readable and writable (both registers)
� Software programmable prescaler (1:1, 1:4, 1:16)
� Software programmable postscaler (1:1 to 1:16)
� Interrupt on TMR4 match of PR4
Timer4 has a control register shown in Register 15-1.
Timer4 can be shut-off by clearing control bit, TMR4ON
(T4CON<2>), to minimize power consumption. The
prescaler and postscaler selection of Timer4 are also
controlled by this register. Figure 15-1 is a simplified
block diagram of the Timer4 module.

15.1

Timer4 Operation

Timer4 can be used as the PWM time-base for the
PWM mode of the CCP module. The TMR4 register is
readable and writable, and is cleared on any device
RESET. The input clock (F

OSC

/4) has a prescale option

of 1:1, 1:4 or 1:16, selected by control bits
T4CKPS1:T4CKPS0 (T4CON<1:0>). The match out-
put of TMR4 goes through a 4-bit postscaler (which
gives a 1:1 to 1:16 scaling inclusive) to generate a
TMR4 interrupt (latched in flag bit TMR4IF, (PIR3<3>)).
The prescaler and postscaler counters are cleared
when any of the following occurs:
� a write to the TMR4 register
� a write to the T4CON register
� any device RESET (Power-on Reset, MCLR

Reset, Watchdog Timer Reset, or Brown-out
Reset)

TMR4 is not cleared when T4CON is written.

REGISTER 15-1:

T4CON: TIMER4 CONTROL REGISTER

U-0

R/W-0

T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0

bit 7

bit 0

bit 7

Unimplemented: Read as '0'

bit 6-3

T4OUTPS3:T4OUTPS0: Timer4 Output Postscale Select bits

0000

= 1:1 Postscale

0001

= 1:2 Postscale

�
�
�
1111

= 1:16 Postscale

bit 2

TMR4ON: Timer4 On bit

= Timer4 is on

= Timer4 is off

bit 1-0

T4CKPS1:T4CKPS0: Timer4 Clock Prescale Select bits

= Prescaler is 1

= Prescaler is 4

= Prescaler is 16

Legend:
R = Readable bit

W = Writable bit

U = Unimplemented bit, read as `0'

- n = Value at POR

`1' = Bit is set

`0' = Bit is cleared

x = Bit is unknown

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PIC18FXX20

16.0 CAPTURE/COMPARE/PWM

(CCP) MODULES

The PIC18FXX20 devices all have five CCP
(Capture/Compare/PWM) modules. Each module con-
tains a 16-bit register, which can operate as a 16-bit
Capture register, a 16-bit Compare register or a Pulse
Width Modulation (PWM) Master/Slave Duty Cycle reg-
ister. Table 16-1 shows the timer resources of the CCP
module modes.
The operation of all CCP modules are identical, with
the exception of the special event trigger present on
CCP1 and CCP2.

For the sake of clarity, CCP module operation in the fol-
lowing sections is described with respect to CCP1. The
descriptions can be applied (with the exception of the
special event triggers) to any of the modules.

REGISTER 16-1:

CCPxCON REGISTER

Note:

Throughout this section, references to reg-
ister and bit names that may be associated
with a specific CCP module are referred to
generically by the use of `x' or `y' in place of
the specific module number. Thus,
"CCPxCON" might refer to the control reg-
ister for CCP1, CCP2, CCP3, CCP4 or
CCP5.

U-0

R/W-0

DCxB1

DCxB0

CCPxM3

CCPxM2 CCPxM1 CCPxM0

bit 7

bit 0

bit 7-6

Unimplemented: Read as '0'

bit 5-4

DCxB1:DCxB0: PWM Duty Cycle bit 1 and bit 0 for CCP module x
Capture mode:
Unused
Compare mode:
Unused
PWM mode:
These bits are the two LSbits (bit 1 and bit 0) of the 10-bit PWM duty cycle. The eight MSbits
(DCx9:DCx2) of the duty cycle are found in CCPRxL.

bit 3-0

CCPxM3:CCPxM0: CCP Module x Mode Select bits

0000

= Capture/Compare/PWM disabled (resets CCPx module)

0001

= Reserved

0010

= Compare mode, toggle output on match (CCPxIF bit is set)

0011

= Reserved

0100

= Capture mode, every falling edge

0101

= Capture mode, every rising edge

0110

= Capture mode, every 4th rising edge

0111

= Capture mode, every 16th rising edge

1000

= Compare mode,

Initialize CCP pin Low; on compare match, force CCP pin High (CCPIF bit is set)

1001

= Compare mode,

Initialize CCP pin High; on compare match, force CCP pin Low (CCPIF bit is set)

1010

= Compare mode,

Generate software interrupt on compare match (CCPIF bit is set, CCP pin is unaffected)

1011

= Compare mode, trigger special event (CCPIF bit is set):

For CCP1 and CCP2:
Timer1 or Timer3 is reset on event
For all other modules:
CCPx pin is unaffected and is configured as an I/O port
(same as CCPxM<3:0> = 1010, above)

11xx

= PWM mode

Legend:
R = Readable bit

W = Writable bit

U = Unimplemented bit, read as `0'

- n = Value at POR

`1' = Bit is set

`0' = Bit is cleared

x = Bit is unknown

PIC18FXX20

DS39609A-page 150

Advance Information

2003 Microchip Technology Inc.

16.1

CCP Module Configuration

Each Capture/Compare/PWM module is associated
with a control register (generically, CCPxCON) and a
data register (CCPRx). The data register, in turn, is
comprised of two 8-bit registers: CCPRxL (low byte)
and CCPRxH (high byte). All registers are both
readable and writable.

16.1.1

CCP MODULES AND TIMER
RESOURCES

The CCP modules utilize Timers 1, 2, 3 or 4, depending
on the mode selected. Timer1 and Timer3 are available
to modules in Capture or Compare modes, while
Timer2 and Timer4 are available for modules in PWM
mode.

TABLE 16-1:

CCP MODE - TIMER
RESOURCE

The assignment of a particular timer to a module is
determined by the Timer-to-CCP Enable bits in the
T3CON register (Register 14-1, page 143). Depending
on the configuration selected, up to four timers may be
active at once, with modules in the same configuration
(Capture/Compare or PWM) sharing timer resources.
The possible configurations are shown in Figure 16-1.

FIGURE 16-1:

CCP AND TIMER INTERCONNECT CONFIGURATIONS

CCP Mode

Timer Resource

Capture

Compare

PWM

Timer1 or Timer3
Timer1 or Timer3
Timer2 or Timer4

TMR1

CCP5

TMR2

TMR3

TMR4

CCP4

CCP3

CCP2

CCP1

TMR1

TMR2

TMR3

CCP5

TMR4

CCP4

CCP3

CCP2

CCP1

TMR1

TMR2

TMR3

CCP5

TMR4

CCP4

CCP3

CCP2

CCP1

TMR1

TMR2

TMR3

CCP5

TMR4

CCP4

CCP3

CCP2

CCP1

T3CCP<2:1> = 00

T3CCP<2:1> = 01

T3CCP<2:1> = 10

T3CCP<2:1> = 11

Timer1 is used for all Capture
and Compare operations for
all CCP modules. Timer2 is
used for PWM operations for
all CCP modules. Modules
may share either timer
resource as a common
time-base.
Timer3 and Timer4 are not
available.

Timer1 and Timer2 are used
for Capture and Compare or
PWM operations for CCP1
only (depending on selected
mode).
All other modules use either
Timer3 or Timer4. Modules
may share either timer
resource as a common time-
base, if they are in
Capture/Compare or PWM
modes.

Timer1 and Timer2 are used
for Capture and Compare or
PWM operations for CCP1
and CCP2 only (depending on
the mode selected for each
module). Both modules may
use a timer as a common
time-base if they are both in
Capture/Compare or PWM
modes.
The other modules use either
Timer3 or Timer4. Modules
may share either timer
resource as a common time-
base if they are in
Capture/Compare or PWM
modes.

Timer3 is used for all Capture
and Compare operations for
all CCP modules. Timer4 is
used for PWM operations for
all CCP modules. Modules
may share either timer
resource as a common
time-base.
Timer1 and Timer2 are not
available.

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PIC18FXX20

16.2

Capture Mode

In Capture mode, CCPR1H:CCPR1L captures the
16-bit value of the TMR1 or TMR3 registers when an
event occurs on pin RC2/CCP1. An event is defined as
one of the following:
� every falling edge
� every rising edge
� every 4th rising edge
� every 16th rising edge
The event is selected by control bits, CCP1M3:CCP1M0
(CCP1CON<3:0>). When a capture is made, the inter-
rupt request flag bit, CCP1IF (PIR1<2>), is set; it must
be cleared in software. If another capture occurs before
the value in register CCPR1 is read, the old captured
value is overwritten by the new captured value.

16.2.1

CCP PIN CONFIGURATION

In Capture mode, the RC2/CCP1 pin should be
configured as an input by setting the TRISC<2> bit.

16.2.2

TIMER1/TIMER3 MODE SELECTION

The timers that are to be used with the capture feature
(Timer1 and/or Timer3) must be running in Timer mode,
or Synchronized Counter mode. In Asynchronous
Counter mode, the capture operation may not work.
The timer to be used with each CCP module is selected
in the T3CON register (see Section 16.1.1).

16.2.3

SOFTWARE INTERRUPT

When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep bit
CCP1IE (PIE1<2>) clear to avoid false interrupts and
should clear the flag bit, CCP1IF, following any such
change in Operating mode.

16.2.4

CCP PRESCALER

There are four prescaler settings, specified by bits
CCP1M3:CCP1M0. Whenever the CCP module is
turned off or the CCP module is not in Capture mode,
the prescaler counter is cleared. This means that any
RESET will clear the prescaler counter.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared, therefore, the first capture may be from
a non-zero prescaler. Example 16-1 shows the recom-
mended method for switching between capture pres-
calers. This example also clears the prescaler counter
and will not generate the "false" interrupt.

EXAMPLE 16-1:

CHANGING BETWEEN
CAPTURE PRESCALERS

FIGURE 16-2:

CAPTURE MODE OPERATION BLOCK DIAGRAM

Note:

If the RC2/CCP1 is configured as an out-
put, a write to the port can cause a capture
condition.

CLRF

CCP1CON, F ; Turn CCP module off

MOVLW

NEW_CAPT_PS ; Load WREG with the

; new prescaler mode

; value and CCP ON

MOVWF CCP1CON

; Load CCP1CON with

; this value

CCPR1H

CCPR1L

TMR1H

TMR1L

Set Flag bit CCP1IF

TMR3
Enable

Q's

CCP1CON<3:0>

CCP1 pin

Prescaler
� 1, 4, 16

and

Edge Detect

TMR3H

TMR3L

TMR1
Enable

T3CCP2

PIC18FXX20

DS39609A-page 152

Advance Information

2003 Microchip Technology Inc.

16.3

Compare Mode

In Compare mode, the 16-bit CCPR1 register value is
constantly compared against either the TMR1 register
pair value, or the TMR3 register pair value. When a
match occurs, the CCP1 pin is:
� driven High
� driven Low
� toggle output (High to Low or Low to High)
� remains unchanged
The action on the pin is based on the value of control
bits, CCP1M3:CCP1M0. At the same time, interrupt
flag bit CCP1IF (CCP2IF) is set.

16.3.1

CCP PIN CONFIGURATION

The user must configure the CCPx pin as an output by
clearing the appropriate TRIS bit.

16.3.2

TIMER1/TIMER3 MODE SELECTION

Timer1 and/or Timer3 must be running in Timer mode,
or Synchronized Counter mode, if the CCP module is
using the compare feature. In Asynchronous Counter
mode, the compare operation may not work.

16.3.3

SOFTWARE INTERRUPT MODE

When generate software interrupt is chosen, the CCP1
pin is not affected. Only a CCP interrupt is generated (if
enabled).

16.3.4

SPECIAL EVENT TRIGGER

In this mode, an internal hardware trigger is generated,
which may be used to initiate an action.
The special event trigger output of either CCP1 or
CCP2, resets the TMR1 or TMR3 register pair, depend-
ing on which timer resource is currently selected. This
allows the CCPR1 register to effectively be a 16-bit
programmable period register for Timer1 or Timer3.
The CCP2 Special Event Trigger will also start an A/D
conversion if the A/D module is enabled.

FIGURE 16-3:

COMPARE MODE OPERATION BLOCK DIAGRAM

Note:

Clearing the CCP1CON register will force
the RC2/CCP1 compare output latch to the
default low level. This is not the PORTC
I/O data latch.

Note:

The special event trigger from the CCP2
module will not set the Timer1 or Timer3
interrupt flag bits.

CCPR1H CCPR1L

TMR1H

TMR1L

Comparator

Output

Logic

Special Event Trigger

Set Flag bit CCP1IF

Match

RC2/CCP1 pin

TRISC<2>

CCP1CON<3:0>

Mode Select

Output Enable

For CCP1 and CCP2 only, the Special Event Trigger will:

Reset Timer1 or Timer3, but not set Timer1 or Timer3 interrupt flag bit,
and set bit, GO/DONE (ADCON0<2>)
which starts an A/D conversion (CCP2 only)

TMR3H

TMR3L

T3CCP2

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PIC18FXX20

TABLE 16-2:

REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR,

BOR

Value on

all other

RESETS

INTCON

GIE/GIEH PEIE/GIEL TMR0IE

INT0IE

RBIE

TMR0IF

INT0IF

RBIF

0000 0000

RCON

IPEN

POR

BOR

0--1 11qq

0--q qquu

PIR1

PSPIF

ADIF

RCIF

TXIF

SSPIF

CCP1IF

TMR2IF

TMR1IF 0000 0000 0000 0000

PIE1

PSPIE

ADIE

RCIE

TXIE

SSPIE

CCP1IE

TMR2IE

TMR1IE 0000 0000 0000 0000

IPR1

PSPIP

ADIP

RCIP

TXIP

SSPIP

CCP1IP

TMR2IP

TMR1IP 0111 1111 0111 1111

PIR2

CMIE

EEIE

BCLIF

LVDIF

TMR3IF

CCP2IF -0-0 0000 ---0 0000

PIE2

CMIF

EEIF

BCLIE

LVDIE

TMR3IE

CCP2IE -0-0 0000 ---0 0000

IPR2

CMIP

EEIP

BCLIP

LVDIP

TMR3IP

CCP2IP -1-1 1111 ---1 1111

PIR3

RC2IF

TX2IF

TMR4IF

CCP5IF

CCP4IF

CCP3IF --00 0000 --00 0000

PIE3

RC2IE

TX2IE

TMR4IE

CCP5IE

CCP4IE

CCP3IE --00 0000 --00 0000

IPR3

RC2IP

TX2IP

TMR4IP

CCP5IP

CCP4IP

CCP3IP --11 1111 --11 1111

TRISC

PORTC Data Direction Register

1111 1111

TMR1L

Holding Register for the Least Significant Byte of the 16-bit TMR1 Register

xxxx xxxx

uuuu uuuu

TMR1H

Holding Register for the Most Significant Byte of the 16-bit TMR1 Register

xxxx xxxx

uuuu uuuu

T1CON

RD16

T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 u-uu uuuu

TMR3H

Timer3 Register High Byte

xxxx xxxx

uuuu uuuu

TMR3L

Timer3 Register Low Byte

xxxx xxxx

uuuu uuuu

T3CON

RD16

T3CCP2

T3CKPS1 T3CKPS0

T3CCP1

T3SYNC TMR3CS TMR3ON 0000 0000 uuuu uuuu

CCPRxL

(1)

Capture/Compare/PWM Register x (LSB)

xxxx xxxx

uuuu uuuu

CCPRxH

(1)

Capture/Compare/PWM Register x (MSB)

xxxx xxxx

uuuu uuuu

CCPxCON

(1)

DCxB1

DCxB0

CCPxM3 CCPxM2 CCPxM1 CCPxM0 --00 0000 --00 0000

Legend:

= unknown, u = unchanged, - = unimplemented, read as '0'.

Shaded cells are not used by Capture and Compare, Timer1 or Timer3.

Note 1: Generic term for all of the identical registers of this name for all CCP modules, where `x' identifies the individual module

(CCP1 through CCP5). Bit assignments and RESET values for all registers of the same generic name are identical.

PIC18FXX20

DS39609A-page 154

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16.4

PWM Mode

In Pulse Width Modulation (PWM) mode, the CCP1 pin
produces up to a 10-bit resolution PWM output. Since
the CCP1 pin is multiplexed with the PORTC data latch,
the TRISC<2> bit must be cleared to make the CCP1
pin an output.

Figure 16-4 shows a simplified block diagram of the
CCP module in PWM mode.
For a step-by-step procedure on how to set up the CCP
module for PWM operation, see Section 16.4.3.

FIGURE 16-4:

SIMPLIFIED PWM BLOCK
DIAGRAM

A PWM output (Figure 16-5) has a time-base (period)
and a time that the output stays high (duty cycle). The
frequency of the PWM is the inverse of the period
(1/period).

FIGURE 16-5:

PWM OUTPUT

16.4.1

PWM PERIOD

The PWM period is specified by writing to the PR2
register. The PWM period can be calculated using the
following formula:

PWM period = (PR2) + 1] � 4 � T

OSC

�

(TMR2 prescale value)

PWM frequency is defined as 1 / [PWM period].
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
� TMR2 is cleared
� The CCP1 pin is set (exception: if PWM duty

cycle = 0%, the CCP1 pin will not be set)

� The PWM duty cycle is latched from CCPR1L into

CCPR1H

16.4.2

PWM DUTY CYCLE

The PWM duty cycle is specified by writing to the
CCPR1L register and to the CCP1CON<5:4> bits. Up
to 10-bit resolution is available. The CCPR1L contains
the eight MSbs and the CCP1CON<5:4> contains the
two LSbs. This 10-bit value is represented by
CCPR1L:CCP1CON<5:4>. The following equation is
used to calculate the PWM duty cycle in time:

PWM duty cycle = (CCPR1L:CCP1CON<5:4>) �

OSC

� (TMR2 prescale value)

CCPR1L and CCP1CON<5:4> can be written to at any
time, but the duty cycle value is not latched into
CCPR1H until after a match between PR2 and TMR2
occurs (i.e., the period is complete). In PWM mode,
CCPR1H is a read only register.
The CCPR1H register and a 2-bit internal latch are used
to double-buffer the PWM duty cycle. This double-
buffering is essential for glitchless PWM operation.
When the CCPR1H and 2-bit latch match TMR2, con-
catenated with an internal 2-bit Q clock, or 2 bits of the
TMR2 prescaler, the CCP1 pin is cleared.
The maximum PWM resolution (bits) for a given PWM
frequency is given by the equation:

Note:

Clearing the CCP1CON register will force
the CCP1 PWM output latch to the default
low level. This is not the PORTC I/O data
latch.

CCPR1L

CCPR1H (Slave)

Comparator

TMR2

Comparator

PR2

(Note 1)

Duty Cycle Registers

CCP1CON<5:4>

Clear Timer,

CCP1 pin and

latch D.C.

TRISC<2>

RC2/CCP1

Note: 8-bit timer is concatenated with 2-bit internal Q clock or

2 bits of the prescaler to create 10-bit time-base.

Period

Duty Cycle

TMR2 = PR2

TMR2 = Duty Cycle

TMR2 = PR2

Note:

The Timer2 and Timer4 postscalers (see
Section 13.0) are not used in the determi-
nation of the PWM frequency. The
postscaler could be used to have a servo
update rate at a different frequency than
the PWM output.

Note:

If the PWM duty cycle value is longer than
the PWM period, the CCP1 pin will not be
cleared.

OSC

PWM

---------------

log

( )

log

-----------------------------bits

PWM Resolution (max)

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16.4.3

SETUP FOR PWM OPERATION

The following steps should be taken when configuring
the CCP module for PWM operation:
1.

Set the PWM period by writing to the PR2 register.

Set the PWM duty cycle by writing to the
CCPR1L register and CCP1CON<5:4> bits.

Make the CCP1 pin an output by clearing the
TRISC<2> bit.

Set the TMR2 prescale value and enable Timer2
by writing to T2CON.

Configure the CCP1 module for PWM operation.

TABLE 16-3:

EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz

TABLE 16-4:

REGISTERS ASSOCIATED WITH PWM, TIMER2 AND TIMER4

PWM Frequency

2.44 kHz

9.77 kHz

39.06 kHz

156.25 kHz

312.50 kHz

416.67 kHz

Timer Prescaler (1, 4, 16)

PR2 Value

FFh

3Fh

1Fh

17h

Maximum Resolution (bits)

6.58

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR, BOR

Value on

all other

RESETS

INTCON

GIE/GIEH PEIE/GIEL

TMR0IE

INT0IE

RBIE

TMR0IF

INT0IF

RBIF

0000 0000 0000 0000

RCON

IPEN

POR

BOR

0--1 11qq 0--q qquu

PIR1

PSPIF

ADIF

RCIF

TXIF

SSPIF

CCP1IF

TMR2IF

TMR1IF 0000 0000 0000 0000

PIE1

PSPIE

ADIE

RCIE

TXIE

SSPIE

CCP1IE

TMR2IE

TMR1IE 0000 0000 0000 0000

IPR1

PSPIP

ADIP

RCIP

TXIP

SSPIP

CCP1IP

TMR2IP

TMR1IP 0111 1111 0111 1111

PIR2

CMIE

EEIE

BCLIF

LVDIF

TMR3IF

CCP2IF -0-0 0000 ---0 0000

PIE2

CMIF

EEIF

BCLIE

LVDIE

TMR3IE

CCP2IE -0-0 0000 ---0 0000

IPR2

CMIP

EEIP

BCLIP

LVDIP

TMR3IP

CCP2IP -1-1 1111 ---1 1111

PIR3

RC2IF

TX2IF

TMR4IF

CCP5IF

CCP4IF

CCP3IF --00 0000 --00 0000

PIE3

RC2IE

TX2IE

TMR4IE

CCP5IE

CCP4IE

CCP3IE --00 0000 --00 0000

IPR3

RC2IP

TX2IP

TMR4IP

CCP5IP

CCP4IP

CCP3IP --11 1111 --11 1111

TMR2

Timer2 Module Register

0000 0000 0000 0000

PR2

Timer2 Module Period Register

1111 1111 1111 1111

T2CON

T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000

T3CON

RD16

T3CCP2

T3CKPS1 T3CKPS0

T3CCP1

T3SYNC TMR3CS TMR3ON 0000 0000 uuuu uuuu

TMR4

Timer4 Register

0000 0000 uuuu uuuu

PR4

Timer4 Period Register

1111 1111 uuuu uuuu

T4CON

T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 TMR4ON T4CKPS1 T4CKPS0 -000 0000 uuuu uuuu

CCPRxL

(1)

Capture/Compare/PWM Register x (LSB)

xxxx xxxx uuuu uuuu

CCPRxH

(1)

Capture/Compare/PWM Register x (MSB)

xxxx xxxx uuuu uuuu

CCPxCON

(1)

DCxB1

DCxB0

CCPxM3

CCPxM2 CCPxM1 CCPxM0 --00 0000 --00 0000

Legend:

= unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by PWM, Timer2, or Timer4.

Note 1: Generic term for all of the identical registers of this name for all CCP modules, where `x' identifies the individual module

(CCP1 through CCP5). Bit assignments and RESET values for all registers of the same generic name are identical.

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PIC18FXX20

17.0 MASTER SYNCHRONOUS

SERIAL PORT (MSSP)
MODULE

17.1

Master SSP (MSSP) Module
Overview

The Master Synchronous Serial Port (MSSP) module is
a serial interface, useful for communicating with other
peripheral or microcontroller devices. These peripheral
devices may be serial EEPROMs, shift registers, dis-
play drivers, A/D converters, etc. The MSSP module
can operate in one of two modes:
� Serial Peripheral Interface (SPI)
� Inter-Integrated Circuit (I

- Full Master mode
- Slave mode (with general address call)

The I

C interface supports the following modes in

hardware:
� Master mode
� Multi-Master mode
� Slave mode

17.2

Control Registers

The MSSP module has three associated registers.
These include a status register (SSPSTAT) and two
control registers (SSPCON1 and SSPCON2). The use
of these registers and their individual configuration bits
differ significantly, depending on whether the MSSP
module is operated in SPI or I

C mode.

Additional details are provided under the individual
sections.

17.3

SPI Mode

The SPI mode allows 8 bits of data to be synchronously
transmitted and received simultaneously. All four
modes of SPI are supported. To accomplish communi-
cation, typically three pins are used:
� Serial Data Out (SDO) - RC5/SDO
� Serial Data In (SDI) - RC4/SDI/SDA
� Serial Clock (SCK) - RC3/SCK/SCL/LVDIN
Additionally, a fourth pin may be used when in a Slave
mode of operation:
� Slave Select (SS) - RF7/SS
Figure 17-1 shows the block diagram of the MSSP
module when operating in SPI mode.

FIGURE 17-1:

MSSP BLOCK DIAGRAM
(SPI MODE)

( )

Read

Write

Internal

Data Bus

SSPSR reg

SSPM3:SSPM0

bit0

Shift

Clock

SS Control

Enable

Edge

Select

Clock Select

TMR2 Output

OSC

Prescaler

4, 16, 64

Edge

Select

Data to TX/RX in SSPSR

TRIS bit

SMP:CKE

RC5/SDO

SSPBUF reg

RC4/SDI/SDA

RF7/SS

RC3/SCK/

SCL

PIC18FXX20

DS39609A-page 158

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17.3.1

REGISTERS

The MSSP module has four registers for SPI mode
operation. These are:
� MSSP Control Register1 (SSPCON1)
� MSSP Status Register (SSPSTAT)
� Serial Receive/Transmit Buffer (SSPBUF)
� MSSP Shift Register (SSPSR) - Not directly

accessible

SSPCON1 and SSPSTAT are the control and status
registers in SPI mode operation. The SSPCON1 regis-
ter is readable and writable. The lower 6 bits of the
SSPSTAT are read only. The upper two bits of the
SSPSTAT are read/write.

SSPSR is the shift register used for shifting data in or
out. SSPBUF is the buffer register to which data bytes
are written to or read from.
In receive operations, SSPSR and SSPBUF together
create a double-buffered receiver. When SSPSR
receives a complete byte, it is transferred to SSPBUF
and the SSPIF interrupt is set.
During transmission, the SSPBUF is not double-
buffered. A write to SSPBUF will write to both SSPBUF
and SSPSR.

REGISTER 17-1:

SSPSTAT: MSSP STATUS REGISTER (SPI MODE)

R/W-0

R-0

SMP

CKE

D/A

R/W

bit 7

bit 0

bit 7

SMP: Sample bit
SPI Master mode:
1

= Input data sampled at end of data output time

= Input data sampled at middle of data output time

SPI Slave mode:
SMP must be cleared when SPI is used in Slave mode

bit 6

CKE: SPI Clock Edge Select bit
When CKP = 0:
1

= Data transmitted on rising edge of SCK

= Data transmitted on falling edge of SCK

When CKP = 1:
1

= Data transmitted on falling edge of SCK

= Data transmitted on rising edge of SCK

bit 5

D/A: Data/Address bit
Used in I

C mode only

bit 4

P: STOP bit
Used in I

C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is

cleared.

bit 3

S: START bit
Used in I

C mode only

bit 2

R/W: Read/Write bit information
Used in I

C mode only

bit 1

UA: Update Address bit
Used in I

C mode only

bit 0

BF: Buffer Full Status bit (Receive mode only)

= Receive complete, SSPBUF is full

= Receive not complete, SSPBUF is empty

Legend:
R = Readable bit

W = Writable bit

U = Unimplemented bit, read as `0'

- n = Value at POR

`1' = Bit is set

`0' = Bit is cleared

x = Bit is unknown

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REGISTER 17-2:

SSPCON1: MSSP CONTROL REGISTER1 (SPI MODE)

R/W-0

WCOL

SSPOV

SSPEN

CKP

SSPM3

SSPM2

SSPM1

SSPM0

bit 7

bit 0

bit 7

WCOL: Write Collision Detect bit (Transmit mode only)

= The SSPBUF register is written while it is still transmitting the previous word

(must be cleared in software)

= No collision

bit 6

SSPOV: Receive Overflow Indicator bit
SPI Slave mode:
1

= A new byte is received while the SSPBUF register is still holding the previous data. In case

of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode.The user
must read the SSPBUF, even if only transmitting data, to avoid setting overflow
(must be cleared in software).

= No overflow

Note:

In Master mode, the overflow bit is not set, since each new reception (and
transmission) is initiated by writing to the SSPBUF register.

bit 5

SSPEN: Synchronous Serial Port Enable bit

= Enables serial port and configures SCK, SDO, SDI, and SS as serial port pins

= Disables serial port and configures these pins as I/O port pins

Note:

When enabled, these pins must be properly configured as input or output.

bit 4

CKP: Clock Polarity Select bit

= IDLE state for clock is a high level

= IDLE state for clock is a low level

bit 3-0

SSPM3:SSPM0: Synchronous Serial Port Mode Select bits

0101

= SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin

0100

= SPI Slave mode, clock = SCK pin, SS pin control enabled

0011

= SPI Master mode, clock = TMR2 output/2

0010

= SPI Master mode, clock = F

OSC

/64

0001

= SPI Master mode, clock = F

OSC

/16

0000

= SPI Master mode, clock = F

OSC

Note:

Bit combinations not specifically listed here are either reserved, or implemented in
I

C mode only.

Legend:
R = Readable bit

W = Writable bit

U = Unimplemented bit, read as `0'

- n = Value at POR

`1' = Bit is set

`0' = Bit is cleared

x = Bit is unknown

PIC18FXX20

DS39609A-page 160

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2003 Microchip Technology Inc.

17.3.2

OPERATION

When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits (SSPCON1<5:0> and SSPSTAT<7:6>).
These control bits allow the following to be specified:
� Master mode (SCK is the clock output)
� Slave mode (SCK is the clock input)
� Clock Polarity (IDLE state of SCK)
� Data input sample phase (middle or end of data

output time)

� Clock edge (output data on rising/falling edge of

SCK)

� Clock Rate (Master mode only)
� Slave Select mode (Slave mode only)
The MSSP consists of a transmit/receive Shift Register
(SSPSR) and a buffer register (SSPBUF). The SSPSR
shifts the data in and out of the device, MSb first. The
SSPBUF holds the data that was written to the SSPSR,
until the received data is ready. Once the 8 bits of data
have been received, that byte is moved to the SSPBUF
register. Then the buffer full detect bit, BF
(SSPSTAT<0>), and the interrupt flag bit, SSPIF, are
set. This double-buffering of the received data
(SSPBUF) allows the next byte to start reception before

reading the data that was just received. Any write to the
SSPBUF register during transmission/reception of data
will be ignored, and the write collision detect bit, WCOL
(SSPCON1<7>), will be set. User software must clear
the WCOL bit so that it can be determined if the follow-
ing write(s) to the SSPBUF register completed
successfully.
When the application software is expecting to receive
valid data, the SSPBUF should be read before the next
byte of data to transfer is written to the SSPBUF. Buffer
full bit, BF (SSPSTAT<0>), indicates when SSPBUF
has been loaded with the received data (transmission
is complete). When the SSPBUF is read, the BF bit is
cleared. This data may be irrelevant if the SPI is only a
transmitter. Generally, the MSSP interrupt is used to
determine when the transmission/reception has com-
pleted. The SSPBUF must be read and/or written. If the
interrupt method is not going to be used, then software
polling can be done to ensure that a write collision does
not occur. Example 17-1 shows the loading of the
SSPBUF (SSPSR) for data transmission.
The SSPSR is not directly readable or writable, and
can only be accessed by addressing the SSPBUF reg-
ister. Additionally, the MSSP status register (SSPSTAT)
indicates the various status conditions.

EXAMPLE 17-1:

LOADING THE SSPBUF (SSPSR) REGISTER

LOOP BTFSS SSPSTAT, BF ;Has data been received(transmit complete)?

BRA LOOP ;No

MOVF SSPBUF, W ;WREG reg = contents of SSPBUF

MOVWF RXDATA ;Save in user RAM, if data is meaningful

MOVF TXDATA, W ;W reg = contents of TXDATA

MOVWF SSPBUF ;New data to xmit

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17.3.3

ENABLING SPI I/O

To enable the serial port, SSP Enable bit, SSPEN
(SSPCON1<5>), must be set. To reset or reconfigure
SPI mode, clear the SSPEN bit, re-initialize the
SSPCON registers, and then set the SSPEN bit. This
configures the SDI, SDO, SCK, and SS pins as serial
port pins. For the pins to behave as the serial port func-
tion, some must have their data direction bits (in the
TRIS register) appropriately programmed as follows:
� SDI is automatically controlled by the SPI module
� SDO must have TRISC<5> bit cleared
� SCK (Master mode) must have TRISC<3> bit

cleared

� SCK (Slave mode) must have TRISC<3> bit set
� SS must have TRISF<7> bit set
Any serial port function that is not desired may be
overridden by programming the corresponding data
direction (TRIS) register to the opposite value.

17.3.4

TYPICAL CONNECTION

Figure 17-2 shows a typical connection between two
microcontrollers. The master controller (Processor 1)
initiates the data transfer by sending the SCK signal.
Data is shifted out of both shift registers on their pro-
grammed clock edge, and latched on the opposite
edge of the clock. Both processors should be pro-
grammed to the same Clock Polarity (CKP), then both
controllers would send and receive data at the same
time. Whether the data is meaningful (or dummy data)
depends on the application software. This leads to
three scenarios for data transmission:
� Master sends data

-- Slave sends dummy data

� Master sends data

-- Slave sends data

� Master sends dummy data

-- Slave sends data

FIGURE 17-2:

SPI MASTER/SLAVE CONNECTION

Serial Input Buffer

(SSPBUF)

Shift Register

(SSPSR)

MSb

LSb

SDO

SDI

PROCESSOR 1

SCK

SPI Master SSPM3:SSPM0 = 00xxb

Serial Input Buffer

(SSPBUF)

Shift Register

(SSPSR)

LSb

MSb

SDI

SDO

PROCESSOR 2

SCK

SPI Slave SSPM3:SSPM0 = 010xb

Serial Clock

PIC18FXX20

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17.3.5

MASTER MODE

The master can initiate the data transfer at any time
because it controls the SCK. The master determines
when the slave (Processor 2, Figure 17-2) is to
broadcast data by the software protocol.
In Master mode, the data is transmitted/received as
soon as the SSPBUF register is written to. If the SPI is
only going to receive, the SDO output could be dis-
abled (programmed as an input). The SSPSR register
will continue to shift in the signal present on the SDI pin
at the programmed clock rate. As each byte is
received, it will be loaded into the SSPBUF register as
if a normal received byte (interrupts and status bits
appropriately set). This could be useful in receiver
applications as a "Line Activity Monitor" mode.
The clock polarity is selected by appropriately program-
ming the CKP bit (SSPCON1<4>). This then, would
give waveforms for SPI communication, as shown in

Figure 17-3, Figure 17-5, and Figure 17-6, where the
MSB is transmitted first. In Master mode, the SPI clock
rate (bit rate) is user programmable to be one of the
following:
� F

OSC

/4 (or T

)

� F

OSC

/16 (or 4 � T

)

� F

OSC

/64 (or 16 � T

)

� Timer2 output/2
This allows a maximum data rate (at 40 MHz) of
10.00 Mbps.
Figure 17-3 shows the waveforms for Master mode.
When the CKE bit is set, the SDO data is valid before
there is a clock edge on SCK. The change of the input
sample is shown based on the state of the SMP bit. The
time when the SSPBUF is loaded with the received
data is shown.

FIGURE 17-3:

SPI MODE WAVEFORM (MASTER MODE)

SCK

(CKP = 0

SCK

(CKP = 1

SCK

(CKP = 0

SCK

(CKP = 1

4 Clock

Modes

Input
Sample

Input

Sample

SDI

bit7

bit0

SDO

bit7

bit6

bit5

bit4

bit3

bit2

bit1

bit0

bit7

bit0

SDI

SSPIF

(SMP = 1)

(SMP = 0)

(SMP = 1)

CKE = 1)

CKE = 0)

CKE = 1)

CKE = 0)

(SMP = 0)

Write to

SSPBUF

SSPSR to

SSPBUF

SDO

bit7

bit6

bit5

bit4

bit3

bit2

bit1

bit0

(CKE = 0)

(CKE = 1)

Next Q4 cycle
after Q2

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PIC18FXX20

17.3.6

SLAVE MODE

In Slave mode, the data is transmitted and received as
the external clock pulses appear on SCK. When the
last bit is latched, the SSPIF interrupt flag bit is set.
While in Slave mode, the external clock is supplied by
the external clock source on the SCK pin. This external
clock must meet the minimum high and low times as
specified in the electrical specifications.
While in SLEEP mode, the slave can transmit/receive
data. When a byte is received, the device will wake-up
from SLEEP.

17.3.7

SLAVE SELECT
SYNCHRONIZATION

The SS pin allows a Synchronous Slave mode. The
SPI must be in Slave mode with SS pin control
enabled (SSPCON1<3:0> = 04h). The pin must not
be driven low for the SS pin to function as an input.
The Data Latch must be high. When the SS pin is
low, transmission and reception are enabled and
the SDO pin is driven. When the SS pin goes high,

the SDO pin is no longer driven, even if in the mid-
dle of a transmitted byte, and becomes a floating
output. External pull-up/pull-down resistors may be
desirable, depending on the application.

When the SPI module resets, the bit counter is forced
to `0'. This can be done by either forcing the SS pin to
a high level or clearing the SSPEN bit.
To emulate two-wire communication, the SDO pin can
be connected to the SDI pin. When the SPI needs to
operate as a receiver, the SDO pin can be configured
as an input. This disables transmissions from the SDO.
The SDI can always be left as an input (SDI function),
since it cannot create a bus conflict.

FIGURE 17-4:

SLAVE SYNCHRONIZATION WAVEFORM

Note 1: When the SPI is in Slave mode with SS pin

control enabled (SSPCON<3:0> = 0100),
the SPI module will reset if the SS pin is set
to V

2: If the SPI is used in Slave mode with CKE

set, then the SS pin control must be
enabled.

SCK

(CKP = 1

SCK

(CKP = 0

Input

Sample

SDI

bit7

SDO

bit7

bit6

bit7

SSPIF

Interrupt

(SMP = 0)

CKE = 0)

(SMP = 0)

Write to

SSPBUF

SSPSR to

SSPBUF

Flag

bit0

bit7

bit0

Next Q4 cycle
after Q2

2003 Microchip Technology Inc.

Advance Information

DS39609A-page 165

PIC18FXX20

17.3.8

SLEEP OPERATION

In Master mode, all module clocks are halted and the
transmission/reception will remain in that state until the
device wakes from SLEEP. After the device returns to
normal mode, the module will continue to
transmit/receive data.
In Slave mode, the SPI transmit/receive shift register
operates asynchronously to the device. This allows the
device to be placed in SLEEP mode and data to be
shifted into the SPI transmit/receive shift register.
When all 8 bits have been received, the MSSP interrupt
flag bit will be set and if enabled, will wake the device
from SLEEP.

17.3.9

EFFECTS OF A RESET

A RESET disables the MSSP module and terminates
the current transfer.

17.3.10

BUS MODE COMPATIBILITY

Table 17-1 shows the compatibility between the
standard SPI modes and the states the CKP and CKE
control bits.

TABLE 17-1:

SPI BUS MODES

There is also a SMP bit, which controls when the data
is sampled.

TABLE 17-2:

REGISTERS ASSOCIATED WITH SPI OPERATION

Standard SPI Mode

Terminology

Control Bits State

CKP

CKE

0, 0

0, 1

1, 0

1, 1

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR,

BOR

Value on

all other

RESETS

INTCON

GIE/GIEH PEIE/GIEL TMR0IE

INT0IE

RBIE

TMR0IF

INT0IF

RBIF

0000 0000 0000 0000

PIR1

PSPIF

ADIF

RCIF

TXIF

SSPIF

CCP1IF

TMR2IF

TMR1IF 0000 0000 0000 0000

PIE1

PSPIE

ADIE

RCIE

TXIE

SSPIE

CCP1IE

TMR2IE

TMR1IE 0000 0000 0000 0000

IPR1

PSPIP

ADIP

RCIP

TXIP

SSPIP

CCP1IP

TMR2IP

TMR1IP 0111 1111 0111 1111

TRISC

PORTC Data Direction Register

1111 1111 1111 1111

TRISF

TRISF7

TRISF6

TRISF5

TRISF4

TRISF3

TRISF2

TRISF1

TRISF0 1111 1111 uuuu uuuu

SSPBUF

Synchronous Serial Port Receive Buffer/Transmit Register

xxxx xxxx uuuu uuuu

SSPCON

WCOL

SSPOV

SSPEN

CKP

SSPM3

SSPM2

SSPM1

SSPM0 0000 0000 0000 0000

SSPSTAT

SMP

CKE

D/A

R/W

0000 0000 0000 0000

Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the MSSP in SPI mode.

PIC18FXX20

DS39609A-page 166

Advance Information

2003 Microchip Technology Inc.

17.4

C Mode

The MSSP module in I

C mode fully implements all

master and slave functions (including general call sup-
port) and provides interrupts on START and STOP bits
in hardware to determine a free bus (multi-master
function). The MSSP module implements the standard
mode specifications, as well as 7-bit and 10-bit
addressing.
Two pins are used for data transfer:
� Serial clock (SCL) - RC3/SCK/SCL
� Serial data (SDA) - RC4/SDI/SDA
The user must configure these pins as inputs or outputs
through the TRISC<4:3> bits.

FIGURE 17-7:

MSSP BLOCK DIAGRAM
(I

C MODE)

17.4.1

REGISTERS

The MSSP module has six registers for I

C operation.

These are:
� MSSP Control Register1 (SSPCON1)
� MSSP Control Register2 (SSPCON2)
� MSSP Status Register (SSPSTAT)
� Serial Receive/Transmit Buffer (SSPBUF)
� MSSP Shift Register (SSPSR) - Not directly

accessible

� MSSP Address Register (SSPADD)
SSPCON, SSPCON2 and SSPSTAT are the control
and status registers in I

C mode operation. The

SSPCON and SSPCON2 registers are readable and
writable. The lower 6 bits of the SSPSTAT are read
only. The upper two bits of the SSPSTAT are
read/write.
SSPSR is the shift register used for shifting data in or
out. SSPBUF is the buffer register to which data bytes
are written to or read from.
SSPADD register holds the slave device address
when the SSP is configured in I

C Slave mode. When

the SSP is configured in Master mode, the lower
seven bits of SSPADD act as the baud rate generator
reload value.
In receive operations, SSPSR and SSPBUF together,
create a double-buffered receiver. When SSPSR
receives a complete byte, it is transferred to SSPBUF
and the SSPIF interrupt is set.
During transmission, the SSPBUF is not double-
buffered. A write to SSPBUF will write to both SSPBUF
and SSPSR.

Read

Write

SSPSR reg

Match Detect

SSPADD reg

START and

STOP bit Detect

SSPBUF reg

Internal
Data Bus

Addr Match

Set, Reset
S, P bits

(SSPSTAT reg)

RC3/SCK/SCL

RC4/

Shift
Clock

MSb

SDI/

LSb

SDA

2003 Microchip Technology Inc.

Advance Information

DS39609A-page 167

PIC18FXX20

REGISTER 17-3:

SSPSTAT: MSSP STATUS REGISTER (I

C MODE)

R/W-0

R-0

SMP

CKE

D/A

R/W

bit 7

bit 0

bit 7

SMP: Slew Rate Control bit
In Master or Slave mode:
1

= Slew rate control disabled for Standard Speed mode (100 kHz and 1 MHz)

= Slew rate control enabled for High Speed mode (400 kHz)

bit 6

CKE: SMBus Select bit
In Master or Slave mode:

= Enable SMBus specific inputs

= Disable SMBus specific inputs

bit 5

D/A: Data/Address bit
In Master mode:
Reserved
In Slave mode:
1

= Indicates that the last byte received or transmitted was data

= Indicates that the last byte received or transmitted was address

bit 4

P: STOP bit
1

= Indicates that a STOP bit has been detected last

= STOP bit was not detected last

Note:

This bit is cleared on RESET and when SSPEN is cleared.

bit 3

S: START bit
1

= Indicates that a START bit has been detected last

= START bit was not detected last

Note:

This bit is cleared on RESET and when SSPEN is cleared.

bit 2

R/W: Read/Write bit Information (I

C mode only)

In Slave mode:
1

= Read

= Write

Note:

This bit holds the R/W bit information following the last address match. This bit is only
valid from the address match to the next START bit, STOP bit, or not ACK bit.

In Master mode:
1

= Transmit is in progress

= Transmit is not in progress

Note:

ORing this bit with SEN, RSEN, PEN, RCEN, or ACKEN will indicate if the MSSP is
in IDLE mode.

bit 1

UA: Update Address bit (10-bit Slave mode only)
1

= Indicates that the user needs to update the address in the SSPADD register

= Address does not need to be updated

bit 0

BF: Buffer Full Status bit
In Transmit mode:
1

= Receive complete, SSPBUF is full

= Receive not complete, SSPBUF is empty

In Receive mode:
1

= Data transmit in progress (does not include the ACK and STOP bits), SSPBUF is full

= Data transmit complete (does not include the ACK and STOP bits), SSPBUF is empty

Legend:
R = Readable bit

W = Writable bit

U = Unimplemented bit, read as `0'

- n = Value at POR

`1' = Bit is set

`0' = Bit is cleared

x = Bit is unknown

PIC18FXX20

DS39609A-page 168

Advance Information

2003 Microchip Technology Inc.

REGISTER 17-4:

SSPCON1: MSSP CONTROL REGISTER1 (I

C MODE)

R/W-0

WCOL

SSPOV

SSPEN

CKP

SSPM3

SSPM2

SSPM1

SSPM0

bit 7

bit 0

bit 7

WCOL: Write Collision Detect bit
In Master Transmit mode:
1

= A write to the SSPBUF register was attempted while the I

C conditions were not valid for

a transmission to be started (must be cleared in software)

= No collision

In Slave Transmit mode:
1

= The SSPBUF register is written while it is still transmitting the previous word (must be

cleared in software)

= No collision

In Receive mode (Master or Slave modes):
This is a "don't care" bit

bit 6

SSPOV: Receive Overflow Indicator bit
In Receive mode:
1

= A byte is received while the SSPBUF register is still holding the previous byte (must

be cleared in software)

= No overflow

In Transmit mode:
This is a "don't care" bit in Transmit mode

bit 5

SSPEN: Synchronous Serial Port Enable bit
1

= Enables the serial port and configures the SDA and SCL pins as the serial port pins

= Disables serial port and configures these pins as I/O port pins

Note:

When enabled, the SDA and SCL pins must be properly configured as input or output.

bit 4

CKP: SCK Release Control bit
In Slave mode:
1

= Release clock

= Holds clock low (clock stretch), used to ensure data setup time

In Master mode:
Unused in this mode

bit 3-0

SSPM3:SSPM0: Synchronous Serial Port Mode Select bits

1111

= I

C Slave mode, 10-bit address with START and STOP bit interrupts enabled

1110

= I

C Slave mode, 7-bit address with START and STOP bit interrupts enabled

1011

= I

C Firmware Controlled Master mode (Slave IDLE)

1000

= I

C Master mode, clock = F

OSC

/ (4 * (SSPADD+1))

0111

= I

C Slave mode, 10-bit address

0110

= I

C Slave mode, 7-bit address

Note:

Bit combinations not specifically listed here are either reserved, or implemented in
SPI mode only.

Legend:
R = Readable bit

W = Writable bit

U = Unimplemented bit, read as `0'

- n = Value at POR

`1' = Bit is set

`0' = Bit is cleared

x = Bit is unknown

2003 Microchip Technology Inc.

Advance Information

DS39609A-page 169

PIC18FXX20

REGISTER 17-5:

SSPCON2: MSSP CONTROL REGISTER 2 (I

C MODE)

R/W-0

GCEN

ACKSTAT

ACKDT

ACKEN

RCEN

PEN

RSEN

SEN

bit 7

bit 0

bit 7

GCEN: General Call Enable bit (Slave mode only)

= Enable interrupt when a general call address (0000h) is received in the SSPSR

= General call address disabled

bit 6

ACKSTAT: Acknowledge Status bit (Master Transmit mode only)

= Acknowledge was not received from slave

= Acknowledge was received from slave

bit 5

ACKDT: Acknowledge Data bit (Master Receive mode only)

= Not Acknowledge

= Acknowledge

Note:

Value that will be transmitted when the user initiates an Acknowledge sequence at
the end of a receive.

bit 4

ACKEN: Acknowledge Sequence Enable bit (Master Receive mode only)

= Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit.

Automatically cleared by hardware.

= Acknowledge sequence IDLE

bit 3

RCEN: Receive Enable bit (Master Mode only)

= Enables Receive mode for I

= Receive IDLE

bit 2

PEN: STOP Condition Enable bit (Master mode only)

= Initiate STOP condition on SDA and SCL pins. Automatically cleared by hardware.

= STOP condition IDLE

bit 1

RSEN: Repeated START Condition Enabled bit (Master mode only)

= Initiate Repeated START condition on SDA and SCL pins.

Automatically cleared by hardware.

= Repeated START condition IDLE

bit 0

SEN: START Condition Enabled/Stretch Enabled bit
In Master mode:
1

= Initiate START condition on SDA and SCL pins. Automatically cleared by hardware.

= START condition IDLE

In Slave mode:
1

= Clock stretching is enabled for both Slave Transmit and Slave Receive (stretch enabled)

= Clock stretching is disabled

Note:

For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I

C module is not in the IDLE

mode, this bit may not be set (no spooling) and the SSPBUF may not be written (or
writes to the SSPBUF are disabled).

Legend:
R = Readable bit

W = Writable bit

U = Unimplemented bit, read as `0'

- n = Value at POR reset

`1' = Bit is set

`0' = Bit is cleared

x = Bit is unknown

PIC18FXX20

DS39609A-page 170

Advance Information

2003 Microchip Technology Inc.

17.4.2

OPERATION

The MSSP module functions are enabled by setting
MSSP Enable bit, SSPEN (SSPCON<5>).
The SSPCON1 register allows control of the I

C oper-

ation. Four mode selection bits (SSPCON<3:0>) allow
one of the following I

C modes to be selected:

� I

C Master mode, clock = (F

OSC

/ 4) x (SSPADD +1)

� I

C Slave mode (7-bit address)

� I

C Slave mode (10-bit address)

� I

C Slave mode (7-bit address), with START and

STOP bit interrupts enabled

� I

C Slave mode (10-bit address), with START and

STOP bit interrupts enabled

� I

C Firmware controlled master operation, slave

is IDLE

Selection of any I

C mode, with the SSPEN bit set,

forces the SCL and SDA pins to be open drain, pro-
vided these pins are programmed to inputs by setting
the appropriate TRISC bits. To ensure proper operation
of the module, pull-up resistors must be provided
externally to the SCL and SDA pins.

17.4.3

SLAVE MODE

In Slave mode, the SCL and SDA pins must be config-
ured as inputs (TRISC<4:3> set). The MSSP module
will override the input state with the output data when
required (slave-transmitter).
The I

C Slave mode hardware will always generate an

interrupt on an address match. Through the mode
select bits, the user can also choose to interrupt on
START and STOP bits
When an address is matched or the data transfer after
an address match is received, the hardware automati-
cally will generate the Acknowledge (ACK) pulse and
load the SSPBUF register with the received value
currently in the SSPSR register.
Any combination of the following conditions will cause
the MSSP module not to give this ACK pulse:
� The buffer full bit BF (SSPSTAT<0>) was set

before the transfer was received.

� The overflow bit SSPOV (SSPCON<6>) was set

before the transfer was received.

In this case, the SSPSR register value is not loaded
into the SSPBUF, but bit SSPIF (PIR1<3>) is set. The
BF bit is cleared by reading the SSPBUF register, while
bit SSPOV is cleared through software.
The SCL clock input must have a minimum high and
low for proper operation. The high and low times of the
I

C specification, as well as the requirement of the

MSSP module, are shown in timing parameter #100
and parameter #101.

17.4.3.1

Addressing

Once the MSSP module has been enabled, it waits for
a START condition to occur. Following the START con-
dition, the 8-bits are shifted into the SSPSR register. All
incoming bits are sampled with the rising edge of the
clock (SCL) line. The value of register SSPSR<7:1> is
compared to the value of the SSPADD register. The
address is compared on the falling edge of the eighth
clock (SCL) pulse. If the addresses match, and the BF
and SSPOV bits are clear, the following events occur:
1.

The SSPSR register value is loaded into the
SSPBUF register.

The buffer full bit BF is set.

An ACK pulse is generated.

MSSP interrupt flag bit, SSPIF (PIR1<3>), is set
(interrupt is generated, if enabled) on the falling
edge of the ninth SCL pulse.

In 10-bit Address mode, two address bytes need to be
received by the slave. The five Most Significant bits
(MSbs) of the first address byte specify if this is a 10-bit
address. Bit R/W (SSPSTAT<2>) must specify a write
so the slave device will receive the second address
byte. For a 10-bit address, the first byte would equal
`11110 A9 A8 0', where `A9' and `A8' are the two
MSbs of the address. The sequence of events for 10-bit
address is as follows, with steps 7 through 9 for the
slave-transmitter:
1.

Receive first (high) byte of Address (bits SSPIF,
BF and bit UA (SSPSTAT<1>) are set).

Update the SSPADD register with second (low)
byte of Address (clears bit UA and releases the
SCL line).

Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.

Receive second (low) byte of Address (bits
SSPIF, BF, and UA are set).

Update the SSPADD register with the first (high)
byte of Address. If match releases SCL line, this
will clear bit UA.

Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.

Receive Repeated START condition.

Receive first (high) byte of Address (bits SSPIF
and BF are set).

Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.

2003 Microchip Technology Inc.

Advance Information

DS39609A-page 171

PIC18FXX20

17.4.3.2

Reception

When the R/W bit of the address byte is clear and an
address match occurs, the R/W bit of the SSPSTAT
register is cleared. The received address is loaded into
the SSPBUF register and the SDA line is held low
(ACK).
When the address byte overflow condition exists, then
the No Acknowledge (ACK) pulse is given. An overflow
condition is defined as either bit BF (SSPSTAT<0>) is
set, or bit SSPOV (SSPCON1<6>) is set.
An MSSP interrupt is generated for each data transfer
byte. Flag bit SSPIF (PIR1<3>) must be cleared in soft-
ware. The SSPSTAT register is used to determine the
status of the byte.
If SEN is enabled (SSPCON1<0> = 1), RC3/SCK/SCL
will be held low (clock stretch) following each data
transfer. The clock must be released by setting bit CKP
(SSPCON<4>). See Section 17.4.4 ("Clock
Stretching"), for more detail.

17.4.3.3

Transmission

When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPSTAT register is set. The received address is
loaded into the SSPBUF register. The ACK pulse will
be sent on the ninth bit and pin RC3/SCK/SCL is held
low, regardless of SEN (see "Clock Stretching",
Section 17.4.4, for more detail). By stretching the clock,
the master will be unable to assert another clock pulse
until the slave is done preparing the transmit data.The
transmit data must be loaded into the SSPBUF register,
which also loads the SSPSR register. Then pin
RC3/SCK/SCL should be enabled by setting bit CKP
(SSPCON1<4>). The eight data bits are shifted out on
the falling edge of the SCL input. This ensures that the
SDA signal is valid during the SCL high time
(Figure 17-9).

The ACK pulse from the master-receiver is latched on
the rising edge of the ninth SCL input pulse. If the SDA
line is high (not ACK), then the data transfer is com-
plete. In this case, when the ACK is latched by the
slave, the slave logic is reset (resets SSPSTAT regis-
ter) and the slave monitors for another occurrence of
the START bit. If the SDA line was low (ACK), the next
transmit data must be loaded into the SSPBUF register.
Again, pin RC3/SCK/SCL must be enabled by setting
bit CKP.
An MSSP interrupt is generated for each data transfer
byte. The SSPIF bit must be cleared in software and
the SSPSTAT register is used to determine the status
of the byte. The SSPIF bit is set on the falling edge of
the ninth clock pulse.

PIC18FXX20

DS39609A-page 174

Advance Information

2003 Microchip Technology Inc.

FIGURE 17-10:

C SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESS)

SDA

SCL

(

SPS

T
A

)

i
v
e
Da

t
a

Byte

ACK

R/W

ACK

ceive F

i
r
s
t B

y
te of A

d
r
ess

l
ea

r
e

d i

f
t
w

r
e

)

l
ear

ed i

ftw

are

i
v
e
S

e
cond B

y
te

of A

ddre

s
s

l
e
a

red

by har

are

h
en S

i
s

update

i
th

l
o

byte

of add

ress

UA (

PST

o
ck is h

l
d

w u

t
il

updat

e of S

has

ken pl

a
c
e

set indicat

i
n
g

tha

the S

need

s to be

upda

ted

is set

i
n
dicating

that

need

s to be

t
ed

l
e

a
r
ed

by har

are

hen

SSP

ADD is u

a
te

with

i
g

b
y
te of

addr

ess

SPB

is wr

itte

n
wi

t
h

conten

ts o

f
S

u
m

y

r
e

d
o

f
SS

PBUF

to clear

flag

CKP

ive

y
te

u
s M

ste

term

i
nates

tran

sfer

ACK

Cle

r
e
d

f
t
wa

r
e

Cle

r
e
d

ft
w

a
r
e

SSP

(

SPCO

6
>

)

SPO

e
t

c
a

SPB

stil

l f

ll. AC

i
s
no

t sent.

(
C

es not

reset

to `

'
w

hen

)

Clo

ck is h

w u

t
il

upda

t
e of

has

t
a

ken p

l
a
c
e

2003 Microchip Technology Inc.

Advance Information

DS39609A-page 175

PIC18FXX20

FIGURE 17-11:

C SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS)

SDA

SCL

SSP

I
F

BF (

PST

0
>)

R/W

ACK

e
ceive F

i
r
s
t B

y
te of

d
r
ess

Cle

r
e
d

f
t
wa

r
e

s M

a
ster

term

i
nates

tran

sfer

)

i
v
e
S

e
cond B

y
te

of A

ddre

s
s

l
e

ed by

hard

are w

h
en

i
s
u

pdate

i
t
h l

byte

of ad

dress

UA (

PST

Clo

ck is h

w u

n
til

date o

f
S

t
a

ken

place

is se

t indicatin

that

the S

need

s to be

upda

ted

is set

indicating

that

need

s to be

u
pdate

Cle

a
r
e

y
h

r
d

r
e
wh

SSP

ADD is u

a
t
e

with

i
g

t
e

f
ad

r
es

PBUF

is wr

i
t
te

with

cont

ent

s of S

y
r

e
a

f
SSP

BUF

to cle

r B

f
l
a
g

Receive F

i
rst B

y
te

of A

dre

s
s

r
an

smitting D

a
ta

y
t
e

y
re

ad of

to cle

r B

f
l
a
g

Cle

a
r
e

ftwa

r
e

r
it
e
o

f
SS

PBUF

itia

t
e

s tr

a
n

l
ea

r
e

d i

f
t
w

r
e

tio

clear

s
B

flag

KP (

SSP

N<4

)

is set in

software

P is a

t
o

tica

l
l
y

e
a

r
e

d
in

r
d

r
e
, h

L
lo

Clo

ck is h

w u

t
il

upd

ate of

has

t
a

ken p

l
ace

tran

smission

Clo

ck is h

w u

n
til

is set to

`
1
'

f
l
a
g

is clear

i
r
d ad

dress s

quen

the e

d of t

PIC18FXX20

DS39609A-page 176

Advance Information

2003 Microchip Technology Inc.

17.4.4

CLOCK STRETCHING

Both 7- and 10-bit Slave modes implement automatic
clock stretching during a transmit sequence.
The SEN bit (SSPCON2<0>) allows clock stretching to
be enabled during receives. Setting SEN will cause
the SCL pin to be held low at the end of each data
receive sequence.

17.4.4.1

Clock Stretching for 7-bit Slave
Receive Mode (SEN = 1)

In 7-bit Slave Receive mode, on the falling edge of the
ninth clock at the end of the ACK sequence, if the BF
bit is set, the CKP bit in the SSPCON1 register is auto-
matically cleared, forcing the SCL output to be held
low. The CKP being cleared to `0' will assert the SCL
line low. The CKP bit must be set in the user's ISR
before reception is allowed to continue. By holding the
SCL line low, the user has time to service the ISR and
read the contents of the SSPBUF before the master
device can initiate another receive sequence. This will
prevent buffer overruns from occurring (see
Figure 17-13).

17.4.4.2

Clock Stretching for 10-bit Slave
Receive Mode (SEN = 1)

In 10-bit Slave Receive mode, during the address
sequence, clock stretching automatically takes place
but CKP is not cleared. During this time, if the UA bit is
set after the ninth clock, clock stretching is initiated.
The UA bit is set after receiving the upper byte of the
10-bit address, and following the receive of the second
byte of the 10-bit address with the R/W bit cleared to
`0'. The release of the clock line occurs upon updating
SSPADD. Clock stretching will occur on each data
receive sequence, as described in 7-bit mode.

17.4.4.3

Clock Stretching for 7-bit Slave
Transmit Mode

7-bit Slave Transmit mode implements clock stretching
by clearing the CKP bit after the falling edge of the
ninth clock, if the BF bit is clear. This occurs,
regardless of the state of the SEN bit.
The user's ISR must set the CKP bit before transmis-
sion is allowed to continue. By holding the SCL line
low, the user has time to service the ISR and load the
contents of the SSPBUF before the master device can
initiate another transmit sequence (see Figure 17-9).

17.4.4.4

Clock Stretching for 10-bit Slave
Transmit Mode

In 10-bit Slave Transmit mode, clock stretching is con-
trolled during the first two address sequences by the
state of the UA bit, just as it is in 10-bit Slave Receive
mode. The first two addresses are followed by a third
address sequence, which contains the high order bits
of the 10-bit address and the R/W bit set to `1'. After
the third address sequence is performed, the UA bit is
not set, the module is now configured in Transmit
mode, and clock stretching is controlled by the BF flag,
as in 7-bit Slave Transmit mode (see Figure 17-11).

Note 1: If the user reads the contents of the

SSPBUF before the falling edge of the
ninth clock, thus clearing the BF bit, the
CKP bit will not be cleared and clock
stretching will not occur.

2: The CKP bit can be set in software,

regardless of the state of the BF bit. The
user should be careful to clear the BF bit
in the ISR before the next receive
sequence, in order to prevent an overflow
condition.

Note:

If the user polls the UA bit and clears it by
updating the SSPADD register before the
falling edge of the ninth clock occurs, and if
the user hasn't cleared the BF bit by read-
ing the SSPBUF register before that time,
then the CKP bit will still NOT be asserted
low. Clock stretching on the basis of the
state of the BF bit only occurs during a data
sequence, not an address sequence.

Note 1: If the user loads the contents of SSPBUF,

setting the BF bit before the falling edge of
the ninth clock, the CKP bit will not be
cleared and clock stretching will not occur.

2: The CKP bit can be set in software,

regardless of the state of the BF bit.

2003 Microchip Technology Inc.

Advance Information

DS39609A-page 179

PIC18FXX20

FIGURE 17-14:

C SLAVE MODE TIMING SEN = 1 (RECEPTION, 10-BIT ADDRESS)

SPI

(

PST

ive

t
a
B

y
te

R/W

ACK

Receive F

i
rst B

y
te o

f
A

ddre

s
s

l
ea

r
e

d i

f
t
w

)

l
ea

r
e

d i

f
t
w

cei

v
e S

nd B

y
te of

d
r
ess

l
e

a
r
ed

by har

are

i
s
upda

ted w

i
t
h

l
o
w

b
y
te of

addr

ess afte

r fal

l
i
ng

edge

(

SPS

T
A

)

Clo

ck is h

w u

n
til

date o

f
S

t
a

ken

ace

i
s
set

i
n
di

cati

that

e S

eeds to

u
pdate

is se

t indicatin

that

s
t

upda

ted

Cle

r
e

y
h

r
d

r
e

e
n

i
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u

date

i
t
h hi

y
te

f
a

d
d

r
e

ss a

fte

r

fa

llin

d
g

SSP

BUF is

it
t
e

i
t
h

ntent

s o

f
S

y
r

d
o

f
SS

PBUF

to clear

flag

ive

t
a

Byte

s M

ster

term

inates

tran

sfer

Clea

r
ed i

n

softwar

l
ea

r
e

d i

f
t
w

r
e

V (

SSP

N<6

)

written

to `1'

t
e

date

of th

e S

r
e

i
ste

r
b

r
e
t

llin

ge of

the n

i
nth cl

ock

i
l
l

ve no ef

ct on U

, and

UA will

r
e

t
e

date of the

r
egiste

r
b

fore

the

l
ling

e
dge

of the

ninth

clock will

h
a

ve no

e
f
fect on U

, and

UA will r

e
m

in softwar

Clo

ck is h

l
d

l
o
w u

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il

upda

te of S

has

k
e

of n

i
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ock

o
f
ni

nth

ock

V is

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c
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ead of

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a

r B

flag

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Clo

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b
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cause

PIC18FXX20

DS39609A-page 180

Advance Information

2003 Microchip Technology Inc.

17.4.5

GENERAL CALL ADDRESS
SUPPORT

The addressing procedure for the I

C bus is such that

the first byte after the START condition usually deter-
mines which device will be the slave addressed by the
master. The exception is the general call address,
which can address all devices. When this address is
used, all devices should, in theory, respond with an
Acknowledge.
The general call address is one of eight addresses
reserved for specific purposes by the I

C protocol. It

consists of all 0's with R/W = 0.
The general call address is recognized when the Gen-
eral Call Enable bit (GCEN) is enabled (SSPCON2<7>
set). Following a START bit detect, 8-bits are shifted
into the SSPSR and the address is compared against
the SSPADD. It is also compared to the general call
address and fixed in hardware.

If the general call address matches, the SSPSR is
transferred to the SSPBUF, the BF flag bit is set (eighth
bit), and on the falling edge of the ninth bit (ACK bit),
the SSPIF interrupt flag bit is set.
When the interrupt is serviced, the source for the inter-
rupt can be checked by reading the contents of the
SSPBUF. The value can be used to determine if the
address was device specific or a general call address.
In 10-bit mode, the SSPADD is required to be updated
for the second half of the address to match, and the UA
bit is set (SSPSTAT<1>). If the general call address is
sampled when the GCEN bit is set, while the slave is
configured in 10-bit Address mode, then the second
half of the address is not necessary, the UA bit will not
be set, and the slave will begin receiving data after the
Acknowledge (Figure 17-15).

FIGURE 17-15:

SLAVE MODE GENERAL CALL ADDRESS SEQUENCE
(7 OR 10-BIT ADDRESS MODE)

SDA

SCL

SSPIF

BF (SSPSTAT<0>)

SSPOV (SSPCON1<6>)

Cleared in software

SSPBUF is read

R/W = 0

ACK

General Call Address

Address is compared to General Call Address

GCEN (SSPCON2<7>)

Receiving Data

ACK

after ACK, set interrupt

'0'

'1'

2003 Microchip Technology Inc.

Advance Information

DS39609A-page 181

PIC18FXX20

17.4.6

MASTER MODE

Master mode is enabled by setting and clearing the
appropriate SSPM bits in SSPCON1 and by setting the
SSPEN bit. In Master mode, the SCL and SDA lines
are manipulated by the MSSP hardware.
Master mode of operation is supported by interrupt
generation on the detection of the START and STOP
conditions. The STOP (P) and START (S) bits are
cleared from a RESET, or when the MSSP module is
disabled. Control of the I

C bus may be taken when the

P bit is set or the bus is IDLE, with both the S and P bits
clear.
In Firmware Controlled Master mode, user code con-
ducts all I

C bus operations based on START and

STOP bit conditions.
Once Master mode is enabled, the user has six
options.
1.

Assert a START condition on SDA and SCL.

Assert a Repeated START condition on SDA
and SCL.

Write to the SSPBUF register initiating
transmission of data/address.

Configure the I

C port to receive data.

Generate an Acknowledge condition at the end
of a received byte of data.

Generate a STOP condition on SDA and SCL.

The following events will cause SSP interrupt flag bit,
SSPIF, to be set (SSP interrupt if enabled):
� START condition
� STOP condition
� Data transfer byte transmitted/received
� Acknowledge Transmit
� Repeated START

FIGURE 17-16:

MSSP BLOCK DIAGRAM (I

C MASTER MODE)

Note:

The MSSP Module, when configured in I

Master mode, does not allow queueing of
events. For instance, the user is not
allowed to initiate a START condition and
immediately write the SSPBUF register to
initiate transmission before the START
condition is complete. In this case, the
SSPBUF will not be written to and the
WCOL bit will be set, indicating that a write
to the SSPBUF did not occur.

Read

Write

SSPSR

START bit, STOP bit,

START bit Detect

SSPBUF

Internal

Data Bus

Set/Reset, S, P, WCOL (SSPSTAT)

Shift

Clock

MSb

LSb

SDA

Acknowledge

Generate

STOP bit Detect

Write Collision Detect

Clock Arbitration

State Counter for

end of XMIT/RCV

SCL

SCL In

Bus Collision

SDA In

Receive Enable

Cloc

k
Cnt

Clock

r
bit

r
at

Det

(hold

f
clock sour

ce)

SSPADD<6:0>

Baud

Set SSPIF, BCLIF
Reset ACKSTAT, PEN (SSPCON2)

Rate

Generator

SSPM3:SSPM0

PIC18FXX20

DS39609A-page 182

Advance Information

2003 Microchip Technology Inc.

17.4.6.1

C Master Mode Operation

The master device generates all of the serial clock
pulses and the START and STOP conditions. A trans-
fer is ended with a STOP condition or with a Repeated
START condition. Since the Repeated START condi-
tion is also the beginning of the next serial transfer, the
I

C bus will not be released.

In Master Transmitter mode, serial data is output
through SDA, while SCL outputs the serial clock. The
first byte transmitted contains the slave address of the
receiving device (7 bits) and the Read/Write (R/W) bit.
In this case, the R/W bit will be logic '0'. Serial data is
transmitted 8 bits at a time. After each byte is transmit-
ted, an Acknowledge bit is received. START and STOP
conditions are output to indicate the beginning and the
end of a serial transfer.
In Master Receive mode, the first byte transmitted con-
tains the slave address of the transmitting device
(7 bits) and the R/W bit. In this case, the R/W bit will be
logic '1'. Thus, the first byte transmitted is a 7-bit slave
address followed by a '1' to indicate receive bit. Serial
data is received via SDA, while SCL outputs the serial
clock. Serial data is received 8 bits at a time. After each
byte is received, an Acknowledge bit is transmitted.
START and STOP conditions indicate the beginning
and end of transmission.
The baud rate generator used for the SPI mode opera-
tion is used to set the SCL clock frequency for either
100 kHz, 400 kHz or 1 MHz I

C operation. See

Section 17.4.7 ("Baud Rate Generator"), for more
detail.

A typical transmit sequence would go as follows:
1.

The user generates a START condition by set-
ting the START enable bit, SEN
(SSPCON2<0>).

SSPIF is set. The MSSP module will wait the
required start time before any other operation
takes place.

The user loads the SSPBUF with the slave
address to transmit.

Address is shifted out the SDA pin until all 8 bits
are transmitted.

The MSSP Module shifts in the ACK bit from the
slave device and writes its value into the
SSPCON2 register (SSPCON2<6>).

The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the SSPIF
bit.

The user loads the SSPBUF with eight bits of
data.

Data is shifted out the SDA pin until all 8 bits are
transmitted.

The MSSP Module shifts in the ACK bit from the
slave device and writes its value into the
SSPCON2 register (SSPCON2<6>).

10. The MSSP module generates an interrupt at the

end of the ninth clock cycle by setting the SSPIF
bit.

11. The user generates a STOP condition by setting

the STOP enable bit PEN (SSPCON2<2>).

12. Interrupt is generated once the STOP condition

is complete.

2003 Microchip Technology Inc.

Advance Information

DS39609A-page 185

PIC18FXX20

17.4.8

C MASTER MODE START

CONDITION TIMING

To initiate a START condition, the user sets the START
condition enable bit, SEN (SSPCON2<0>). If the SDA
and SCL pins are sampled high, the baud rate genera-
tor is reloaded with the contents of SSPADD<6:0> and
starts its count. If SCL and SDA are both sampled high
when the baud rate generator times out (T

BRG

), the

SDA pin is driven low. The action of the SDA being
driven low, while SCL is high, is the START condition
and causes the S bit (SSPSTAT<3>) to be set. Follow-
ing this, the baud rate generator is reloaded with the
contents of SSPADD<6:0> and resumes its count.
When the baud rate generator times out (T

BRG

), the

SEN bit (SSPCON2<0>) will be automatically cleared
by hardware, the baud rate generator is suspended,
leaving the SDA line held low and the START condition
is complete.

17.4.8.1

WCOL Status Flag

If the user writes the SSPBUF when a START
sequence is in progress, the WCOL is set and the con-
tents of the buffer are unchanged (the write doesn't
occur).

FIGURE 17-19:

FIRST START BIT TIMING

Note:

If at the beginning of the START condition,
the SDA and SCL pins are already sam-
pled low, or if during the START condition
the SCL line is sampled low before the
SDA line is driven low, a bus collision
occurs, the Bus Collision Interrupt Flag,
BCLIF is set, the START condition is
aborted, and the I

C module is reset into its

IDLE state.

Note:

Because queueing of events is not
allowed, writing to the lower 5 bits of
SSPCON2 is disabled until the START
condition is complete.

SDA

SCL

BRG

1st bit

2nd bit

BRG

SDA = 1,

At completion of START bit,

SCL = 1

Write to SSPBUF occurs here

BRG

hardware clears SEN bit

BRG

Write to SEN bit occurs here

Set S bit (SSPSTAT<3>)

and sets SSPIF bit

PIC18FXX20

DS39609A-page 186

Advance Information

2003 Microchip Technology Inc.

17.4.9

C MASTER MODE REPEATED

START CONDITION TIMING

A Repeated START condition occurs when the RSEN
bit (SSPCON2<1>) is programmed high and the I

logic module is in the IDLE state. When the RSEN bit is
set, the SCL pin is asserted low. When the SCL pin is
sampled low, the baud rate generator is loaded with the
contents of SSPADD<5:0> and begins counting. The
SDA pin is released (brought high) for one baud rate
generator count (T

BRG

). When the baud rate generator

times out, if SDA is sampled high, the SCL pin will be
de-asserted (brought high). When SCL is sampled
high, the baud rate generator is reloaded with the con-
tents of SSPADD<6:0> and begins counting. SDA and
SCL must be sampled high for one T

BRG

. This action is

then followed by assertion of the SDA pin (SDA = 0) for
one T

BRG,

while SCL is high. Following this, the RSEN

bit (SSPCON2<1>) will be automatically cleared and
the baud rate generator will not be reloaded, leaving
the SDA pin held low. As soon as a START condition is
detected on the SDA and SCL pins, the S bit
(SSPSTAT<3>) will be set. The SSPIF bit will not be set
until the baud rate generator has timed out.

Immediately following the SSPIF bit getting set, the
user may write the SSPBUF with the 7-bit address in
7-bit mode, or the default first address in 10-bit mode.
After the first eight bits are transmitted and an ACK is
received, the user may then transmit an additional eight
bits of address (10-bit mode) or eight bits of data (7-bit
mode).

17.4.9.1

WCOL Status Flag

If the user writes the SSPBUF when a Repeated
START sequence is in progress, the WCOL is set and
the contents of the buffer are unchanged (the write
doesn't occur).

FIGURE 17-20:

REPEAT START CONDITION WAVEFORM

Note 1: If RSEN is programmed while any other

event is in progress, it will not take effect.

2: A bus collision during the Repeated

START condition occurs if:

� SDA is sampled low when SCL goes

from low to high.

� SCL goes low before SDA is

asserted low. This may indicate that
another master is attempting to
transmit a data "1".

Note:

Because queueing of events is not
allowed, writing of the lower 5 bits of
SSPCON2 is disabled until the Repeated
START condition is complete.

SDA

SCL

Sr = Repeated START

Write to SSPCON2

Write to SSPBUF occurs here

Falling edge of ninth clock

End of Xmit

At completion of START bit,
hardware clears RSEN bit

1st bit

Set S (SSPSTAT<3>)

BRG

SDA = 1,

SCL (no change).

SCL = 1

occurs here.

BRG

and sets SSPIF

2003 Microchip Technology Inc.

Advance Information

DS39609A-page 187

PIC18FXX20

17.4.10

C MASTER MODE

TRANSMISSION

Transmission of a data byte, a 7-bit address, or the
other half of a 10-bit address is accomplished by simply
writing a value to the SSPBUF register. This action will
set the buffer full flag bit, BF, and allow the baud rate
generator to begin counting and start the next transmis-
sion. Each bit of address/data will be shifted out onto
the SDA pin after the falling edge of SCL is asserted
(see data hold time specification parameter #106). SCL
is held low for one baud rate generator rollover count
(T

BRG

). Data should be valid before SCL is released

high (see data setup time specification parameter
#107). When the SCL pin is released high, it is held that
way for T

BRG

. The data on the SDA pin must remain

stable for that duration and some hold time, after the
next falling edge of SCL. After the eighth bit is shifted
out (the falling edge of the eighth clock), the BF flag is
cleared and the master releases SDA. This allows the
slave device being addressed to respond with an ACK
bit during the ninth bit time if an address match
occurred, or if data was received properly. The status
of ACK is written into the ACKDT bit on the falling edge
of the ninth clock. If the master receives an Acknowl-
edge, the Acknowledge status bit, ACKSTAT, is
cleared. If not, the bit is set. After the ninth clock, the
SSPIF bit is set and the master clock (baud rate gener-
ator) is suspended until the next data byte is loaded into
the SSPBUF, leaving SCL low and SDA unchanged
(Figure 17-21).
After the write to the SSPBUF, each bit of address will
be shifted out on the falling edge of SCL, until all seven
address bits and the R/W bit are completed. On the fall-
ing edge of the eighth clock, the master will de-assert
the SDA pin, allowing the slave to respond with an
Acknowledge. On the falling edge of the ninth clock, the
master will sample the SDA pin to see if the address
was recognized by a slave. The status of the ACK bit is
loaded into the ACKSTAT status bit (SSPCON2<6>).
Following the falling edge of the ninth clock transmis-
sion of the address, the SSPIF is set, the BF flag is
cleared and the baud rate generator is turned off until
another write to the SSPBUF takes place, holding SCL
low and allowing SDA to float.

17.4.10.1

BF Status Flag

In Transmit mode, the BF bit (SSPSTAT<0>) is set
when the CPU writes to SSPBUF and is cleared when
all 8 bits are shifted out.

17.4.10.2

WCOL Status Flag

If the user writes the SSPBUF when a transmit is
already in progress (i.e., SSPSR is still shifting out a
data byte), the WCOL is set and the contents of the
buffer are unchanged (the write doesn't occur).
WCOL must be cleared in software.

17.4.10.3

ACKSTAT Status Flag

In Transmit mode, the ACKSTAT bit (SSPCON2<6>) is
cleared when the slave has sent an Acknowledge
(ACK = 0), and is set when the slave does not Acknowl-
edge (ACK = 1). A slave sends an Acknowledge when
it has recognized its address (including a general call),
or when the slave has properly received its data.

17.4.11

C MASTER MODE RECEPTION

Master mode reception is enabled by programming the
receive enable bit, RCEN (SSPCON2<3>).

The baud rate generator begins counting, and on each
rollover, the state of the SCL pin changes (high to
low/low to high) and data is shifted into the SSPSR.
After the falling edge of the eighth clock, the receive
enable flag is automatically cleared, the contents of the
SSPSR are loaded into the SSPBUF, the BF flag bit is
set, the SSPIF flag bit is set and the baud rate genera-
tor is suspended from counting, holding SCL low. The
MSSP is now in IDLE state, awaiting the next com-
mand. When the buffer is read by the CPU, the BF flag
bit is automatically cleared. The user can then send an
Acknowledge bit at the end of reception, by setting the
Acknowledge sequence enable bit, ACKEN
(SSPCON2<4>).

17.4.11.1

BF Status Flag

In receive operation, the BF bit is set when an address
or data byte is loaded into SSPBUF from SSPSR. It is
cleared when the SSPBUF register is read.

17.4.11.2

SSPOV Status Flag

In receive operation, the SSPOV bit is set when 8 bits
are received into the SSPSR and the BF flag bit is
already set from a previous reception.

17.4.11.3

WCOL Status Flag

If the user writes the SSPBUF when a receive is
already in progress (i.e., SSPSR is still shifting in a data
byte), the WCOL bit is set and the contents of the buffer
are unchanged (the write doesn't occur).

Note:

The MSSP module must be in an IDLE
state before the RCEN bit is set, or the
RCEN bit will be disregarded.

2003 Microchip Technology Inc.

Advance Information

DS39609A-page 189

PIC18FXX20

FIGURE 17-22:

C MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS)

SDA

SCL

s M

a
ster

ter

i
nate

tra

sfer

ivin

a
v
e

ivin

g
Da

t
a

o
m

Sla

v
e

ACK

R/W

r
a
n

smi

t
A

ddr

ess to S

l
ave

SSPI

i
s
not

sent

r
it
e

t
o

PCO

(
SEN =

)

r
i
t
e

to S

occu

rs her

K f

r
o

v
e

ster

confi

g
ured

as a r

cei

v
er

b
y
pro

ram

i
n

)

N b

i
t
=

r
i
tte

n her

t
a

i
f
ted i

fal

l
i
ng

edge o

f
C

l
ear

ed i

ftw

are

t
art X

SEN =

SSPO

SDA =

, S

L
=

i
l
e
CP

(
S

PST

st bit is shifte

d into

R an

con

t
ent

s ar

e unl

ded i

n
to S

Cle

r
e
d

ft
w

a
r
e

l
ea

r
e

d i

f
t
w

e
t S

I
F

terr

upt

at en

d of r

cei

v
e

t
P b

i
t

(
SSP

n
d

Cle

r
e

soft

a
r
e

fro

ster

t
SS

F a

t
e

n
d

t S

inter

r
up

end o

f
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cknow

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edge

quence

t
SS

F in

t
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r
r
u

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seque

nce

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ceive

t A

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cknow

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e sequ

ence

i
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set

beca

SPB

is still fu

A = ACK

T =

RCEN cle

r
e

a
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tom

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RCEN =

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ar

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recei

v
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r
ite to

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to st

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cknow

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edge

seque

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SDA = A

KDT

PIC18FXX20

DS39609A-page 190

Advance Information

2003 Microchip Technology Inc.

17.4.12

ACKNOWLEDGE SEQUENCE
TIMING

An Acknowledge sequence is enabled by setting the
Acknowledge sequence enable bit, ACKEN
(SSPCON2<4>). When this bit is set, the SCL pin is
pulled low and the contents of the Acknowledge data bit
are presented on the SDA pin. If the user wishes to gen-
erate an Acknowledge, then the ACKDT bit should be
cleared. If not, the user should set the ACKDT bit before
starting an Acknowledge sequence. The baud rate gen-
erator then counts for one rollover period (T

BRG

) and the

SCL pin is de-asserted (pulled high). When the SCL pin
is sampled high (clock arbitration), the baud rate gener-
ator counts for T

BRG

. The SCL pin is then pulled low. Fol-

lowing this, the ACKEN bit is automatically cleared, the
baud rate generator is turned off and the MSSP module
then goes into IDLE mode (Figure 17-23).

17.4.12.1

WCOL Status Flag

If the user writes the SSPBUF when an Acknowledge
sequence is in progress, then WCOL is set and the con-
tents of the buffer are unchanged (the write doesn't occur).

17.4.13

STOP CONDITION TIMING

A STOP bit is asserted on the SDA pin at the end of a
receive/transmit by setting the STOP sequence enable
bit, PEN (SSPCON2<2>). At the end of a
receive/transmit, the SCL line is held low after the fall-
ing edge of the ninth clock. When the PEN bit is set, the
master will assert the SDA line low. When the SDA line
is sampled low, the baud rate generator is reloaded and
counts down to `0'. When the baud rate generator times
out, the SCL pin will be brought high, and one T

BRG

(baud rate generator rollover count) later, the SDA pin
will be de-asserted. When the SDA pin is sampled high
while SCL is high, the P bit (SSPSTAT<4>) is set. A
T

BRG

later, the PEN bit is cleared and the SSPIF bit is

set (Figure 17-24).

17.4.13.1

WCOL Status Flag

If the user writes the SSPBUF when a STOP sequence
is in progress, then the WCOL bit is set and the con-
tents of the buffer are unchanged (the write doesn't
occur).

FIGURE 17-23:

ACKNOWLEDGE SEQUENCE WAVEFORM

FIGURE 17-24:

STOP CONDITION RECEIVE OR TRANSMIT MODE

Note: T

BRG

= one baud rate generator period.

SDA

SCL

Set SSPIF at the end

Acknowledge sequence starts here,

Write to SSPCON2

ACKEN automatically cleared

Cleared in

BRG

of receive

ACK

ACKEN = 1, ACKDT = 0

SSPIF

software

Set SSPIF at the end
of Acknowledge sequence

Cleared in
software

SCL

SDA

SDA asserted low before rising edge of clock

Write to SSPCON2

Set PEN

Falling edge of

SCL = 1 for T

BRG

, followed by SDA = 1 for T

BRG

9th clock

SCL brought high after T

BRG

Note: T

BRG

= one baud rate generator period.

BRG

after SDA sampled high. P bit (SSPSTAT<4>) is set.

BRG

to setup STOP condition

ACK

BRG

PEN bit (SSPCON2<2>) is cleared by
hardware and the SSPIF bit is set

2003 Microchip Technology Inc.

Advance Information

DS39609A-page 191

PIC18FXX20

17.4.14

SLEEP OPERATION

While in SLEEP mode, the I

C module can receive

addresses or data, and when an address match or
complete byte transfer occurs, wake the processor
from SLEEP (if the MSSP interrupt is enabled).

17.4.15

EFFECT OF A RESET

A RESET disables the MSSP module and terminates
the current transfer.

17.4.16

MULTI-MASTER MODE

In Multi-Master mode, the interrupt generation on the
detection of the START and STOP conditions allows
the determination of when the bus is free. The STOP
(P) and START (S) bits are cleared from a RESET or
when the MSSP module is disabled. Control of the I

bus may be taken when the P bit (SSPSTAT<4>) is set,
or the bus is idle with both the S and P bits clear. When
the bus is busy, enabling the SSP interrupt will
generate the interrupt when the STOP condition
occurs.
In multi-master operation, the SDA line must be moni-
tored for arbitration, to see if the signal level is the
expected output level. This check is performed in
hardware, with the result placed in the BCLIF bit.
The states where arbitration can be lost are:
� Address Transfer
� Data Transfer
� A START Condition
� A Repeated START Condition
� An Acknowledge Condition

17.4.17

MULTI -MASTER COMMUNICATION,
BUS COLLISION, AND BUS
ARBITRATION

Multi-Master mode support is achieved by bus arbitra-
tion. When the master outputs address/data bits onto
the SDA pin, arbitration takes place when the master
outputs a '1' on SDA, by letting SDA float high and
another master asserts a '0'. When the SCL pin floats
high, data should be stable. If the expected data on
SDA is a '1' and the data sampled on the SDA pin = 0,
then a bus collision has taken place. The master will set
the Bus Collision Interrupt Flag, BCLIF and reset the
I

C port to its IDLE state (Figure 17-25).

If a transmit was in progress when the bus collision
occurred, the transmission is halted, the BF flag is
cleared, the SDA and SCL lines are de-asserted, and
the SSPBUF can be written to. When the user services
the bus collision Interrupt Service Routine, and if the
I

C bus is free, the user can resume communication by

asserting a START condition.
If a START, Repeated START, STOP, or Acknowledge
condition was in progress when the bus collision
occurred, the condition is aborted, the SDA and SCL
lines are de-asserted, and the respective control bits in
the SSPCON2 register are cleared. When the user ser-
vices the bus collision Interrupt Service Routine, and if
the I

C bus is free, the user can resume communication

by asserting a START condition.
The master will continue to monitor the SDA and SCL
pins. If a STOP condition occurs, the SSPIF bit will be set.
A write to the SSPBUF will start the transmission of
data at the first data bit, regardless of where the
transmitter left off when the bus collision occurred.
In Multi-Master mode, the interrupt generation on the
detection of START and STOP conditions allows the
determination of when the bus is free. Control of the I

bus can be taken when the P bit is set in the SSPSTAT
register, or the bus is IDLE and the S and P bits are
cleared.

FIGURE 17-25:

BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE

SDA

SCL

BCLIF

SDA released

SDA line pulled low

by another source

Sample SDA. While SCL is high,
data doesn't match what is driven

Bus collision has occurred.

Set bus collision
interrupt (BCLIF)

by the master.

by master

Data changes
while SCL = 0

PIC18FXX20

DS39609A-page 192

Advance Information

2003 Microchip Technology Inc.

17.4.17.1

Bus Collision During a START
Condition

During a START condition, a bus collision occurs if:
a)

SDA or SCL are sampled low at the beginning of
the START condition (Figure 17-26).

SCL is sampled low before SDA is asserted low
(Figure 17-27).

During a START condition, both the SDA and the SCL
pins are monitored.
If the SDA pin is already low, or the SCL pin is already
low, then all of the following occur:
� the START condition is aborted,
� the BCLIF flag is set, and
� the MSSP module is reset to its IDLE state

(Figure 17-26).

The START condition begins with the SDA and SCL
pins de-asserted. When the SDA pin is sampled high,
the baud rate generator is loaded from SSPADD<6:0>
and counts down to `0'. If the SCL pin is sampled low
while SDA is high, a bus collision occurs, because it is
assumed that another master is attempting to drive a
data '1' during the START condition.

If the SDA pin is sampled low during this count, the
BRG is reset and the SDA line is asserted early
(Figure 17-28). If, however, a '1' is sampled on the SDA
pin, the SDA pin is asserted low at the end of the BRG
count. The baud rate generator is then reloaded and
counts down to `0', and during this time, if the SCL pins
are sampled as '0', a bus collision does not occur. At
the end of the BRG count, the SCL pin is asserted low.

FIGURE 17-26:

BUS COLLISION DURING START CONDITION (SDA ONLY)

Note:

The reason that bus collision is not a factor
during a START condition is that no two
bus masters can assert a START condition
at the exact same time. Therefore, one
master will always assert SDA before the
other. This condition does not cause a bus
collision, because the two masters must be
allowed to arbitrate the first address follow-
ing the START condition. If the address is
the same, arbitration must be allowed to
continue into the data portion, Repeated
START or STOP conditions.

SDA

SCL

SEN

SDA sampled low before

SDA goes low before the SEN bit is set.

S bit and SSPIF set because

SSP module reset into IDLE state.

SEN cleared automatically because of bus collision.

S bit and SSPIF set because

Set SEN, enable START

condition if SDA = 1, SCL = 1

SDA = 0, SCL = 1.

BCLIF

SSPIF

SDA = 0, SCL = 1.

SSPIF and BCLIF are

cleared in software

SSPIF and BCLIF are

cleared in software

Set BCLIF,

Set BCLIF.

START condition.

PIC18FXX20

DS39609A-page 194

Advance Information

2003 Microchip Technology Inc.

17.4.17.2

Bus Collision During a Repeated
START Condition

During a Repeated START condition, a bus collision
occurs if:
a)

A low level is sampled on SDA when SCL goes
from low level to high level.

SCL goes low before SDA is asserted low, indi-
cating that another master is attempting to
transmit a data '1'.

When the user de-asserts SDA and the pin is allowed to
float high, the BRG is loaded with SSPADD<6:0> and
counts down to `0'. The SCL pin is then de-asserted,
and when sampled high, the SDA pin is sampled.
If SDA is low, a bus collision has occurred (i.e., another
master is attempting to transmit a data '0',
Figure 17-29). If SDA is sampled high, the BRG is

reloaded and begins counting. If SDA goes from high to
low before the BRG times out, no bus collision occurs
because no two masters can assert SDA at exactly the
same time.
If SCL goes from high to low before the BRG times out
and SDA has not already been asserted, a bus collision
occurs. In this case, another master is attempting to
transmit a data '1' during the Repeated START
condition, Figure 17-30.
If, at the end of the BRG time-out, both SCL and SDA
are still high, the SDA pin is driven low and the BRG is
reloaded and begins counting. At the end of the count,
regardless of the status of the SCL pin, the SCL pin is
driven low and the Repeated START condition is
complete.

FIGURE 17-29:

BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)

FIGURE 17-30:

BUS COLLISION DURING REPEATED START CONDITION (CASE 2)

SDA

SCL

RSEN

BCLIF

SSPIF

Sample SDA when SCL goes high.
If SDA = 0, set BCLIF and release SDA and SCL.

Cleared in software

'0'

SDA

SCL

BCLIF

RSEN

SSPIF

Interrupt cleared
in software

SCL goes low before SDA,
Set BCLIF. Release SDA and SCL.

BRG

'0'

2003 Microchip Technology Inc.

Advance Information

DS39609A-page 197

PIC18FXX20

18.0 ADDRESSABLE UNIVERSAL

SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (USART)

The Universal Synchronous Asynchronous Receiver
Transmitter (USART) module (also known as a Serial
Communications Interface or SCI) is one of the two
types of serial I/O modules available on PIC18FXX20
devices. Each device has two USARTs, which can be
configured independently of each other. Each can be
configured as a full-duplex asynchronous system that
can communicate with peripheral devices, such as
CRT terminals and personal computers, or as a
half-duplex synchronous system that can communicate
with peripheral devices, such as A/D or D/A integrated
circuits, serial EEPROMs, etc.
The USART can be configured in the following modes:
� Asynchronous (full-duplex)
� Synchronous - Master (half-duplex)
� Synchronous - Slave (half-duplex)
The pins of USART1 and USART2 are multiplexed with
the functions of PORTC (RC6/TX1/CK1 and
RC7/RX1/DT1) and PORTG (RG1/TX2/CK2 and
RG2/RX2/DT2), respectively. In order to configure
these pins as a USART:
� For USART1:

- bit SPEN (RCSTA1<7>) must be set (= 1)
- bit TRISC<7> must be set (= 1)
- bit TRISC<6> must be cleared (= 0) for

Asynchronous and Synchronous Master
modes

- bit TRISC<6> must be set (= 1) for

Synchronous Slave mode

� For USART2:

- bit SPEN (RCSTA2<7>) must be set (= 1)
- bit TRISG<2> must be set (= 1)
- bit TRISG<1> must be cleared (= 0) for

Asynchronous and Synchronous Master
modes

- bit TRISC<6> must be set (= 1) for

Synchronous Slave mode

Register 18-1 shows the layout of the Transmit Status
and Control Registers (TXSTAx) and Register 18-2
shows the layout of the Receive Status and Control
Registers (RCSTAx). USART1 and USART2 each
have their own independent and distinct pairs of trans-
mit and receive control registers, which are identical to
each other apart from their names. Similarly, each
USART has its own distinct set of transmit, receive and
baud rate registers.

Note:

Throughout this section, references to reg-
ister and bit names that may be associated
with a specific USART module are referred
to generically by the use of `x' in place of
the specific module number. Thus,
"RCSTAx" might refer to the receive status
register for either USART1 or USART2.

2003 Microchip Technology Inc.

Advance Information

DS39609A-page 199

PIC18FXX20

REGISTER 18-2:

RCSTAx: RECEIVE STATUS AND CONTROL REGISTER

R/W-0

R-0

R-x

SPEN

RX9

SREN

CREN

ADDEN

FERR

OERR

RX9D

bit 7

bit 0

bit 7

SPEN: Serial Port Enable bit
1

= Serial port enabled (configures RX/DT and TX/CK pins as serial port pins)

= Serial port disabled

bit 6

RX9: 9-bit Receive Enable bit
1

= Selects 9-bit reception

= Selects 8-bit reception

bit 5

SREN: Single Receive Enable bit
Asynchronous mode:
Don't care
Synchronous mode - Master:
1

= Enables single receive

= Disables single receive

This bit is cleared after reception is complete.

Synchronous mode - Slave:
Don't care

bit 4

CREN: Continuous Receive Enable bit
Asynchronous mode:
1

= Enables receiver

= Disables receiver

Synchronous mode:
1

= Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)

= Disables continuous receive

bit 3

ADDEN: Address Detect Enable bit
Asynchronous mode 9-bit (RX9 = 1):
1

= Enables address detection, enables interrupt and load of the receive buffer

when RSR<8> is set

= Disables address detection, all bytes are received, and ninth bit can be used as parity bit

bit 2

FERR: Framing Error bit
1

= Framing error (can be updated by reading RCREG register and receive next valid byte)

= No framing error

bit 1

OERR: Overrun Error bit
1

= Overrun error (can be cleared by clearing bit CREN)

= No overrun error

bit 0

RX9D: 9th bit of Received Data
This can be address/data bit or a parity bit, and must be calculated by user firmware

Legend:
R = Readable bit

W = Writable bit

U = Unimplemented bit, read as `0'

- n = Value at POR

`1' = Bit is set

`0' = Bit is cleared

x = Bit is unknown

PIC18FXX20

DS39609A-page 200

Advance Information

2003 Microchip Technology Inc.

18.1

USART Baud Rate Generator
(BRG)

The BRG supports both the Asynchronous and Syn-
chronous modes of the USARTs. It is a dedicated 8-bit
baud rate generator. The SPBRG register controls the
period of a free running 8-bit timer. In Asynchronous
mode, bit BRGH (TXSTAx<2>) also controls the baud
rate. In Synchronous mode, bit BRGH is ignored.
Table 18-1 shows the formula for computation of the
baud rate for different USART modes, which only apply
in Master mode (internal clock).
Given the desired baud rate and F

OSC

, the nearest

integer value for the SPBRGx register can be calcu-
lated using the formula in Table 18-1. From this, the
error in baud rate can be determined.

Example 18-1 shows the calculation of the baud rate
error for the following conditions:
� F

OSC

= 16 MHz

� Desired Baud Rate = 9600
� BRGH = 0
� SYNC = 0
It may be advantageous to use the high baud rate
(BRGH = 1), even for slower baud clocks. This is
because the equation in Example 18-1 can reduce the
baud rate error in some cases.
Writing a new value to the SPBRGx register causes the
BRG timer to be reset (or cleared). This ensures the
BRG does not wait for a timer overflow before
outputting the new baud rate.

18.1.1

SAMPLING

The data on the RXx pin (either RC7/RX1/DT1 or
RG2/RX2/DT2) is sampled three times by a majority
detect circuit to determine if a high or a low level is
present at the pin.

EXAMPLE 18-1:

CALCULATING BAUD RATE ERROR

TABLE 18-1:

BAUD RATE FORMULA

TABLE 18-2:

REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR

Desired Baud Rate

= F

OSC

/ (64 (X + 1))

Solving for X:

= (

OSC

/ Desired Baud Rate) / 64 ) � 1

= ((16000000 / 9600) / 64) � 1

= [25.042] = 25

Calculated Baud Rate

= 16000000 / (64 (25 + 1))
= 9615

Error

= (Calculated Baud Rate - Desired Baud Rate)
Desired Baud Rate
= (9615 � 9600) / 9600
= 0.16%

SYNC

BRGH = 0 (Low Speed)

BRGH = 1 (High Speed)

(Asynchronous) Baud Rate = F

OSC

/(64(X+1))

(Synchronous) Baud Rate = F

OSC

/(4(X+1))

Baud Rate = F

OSC

/(16(X+1))

N/A

Legend: X = value in SPBRGx (0 to 255)

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR, BOR

Value on

all other

RESETS

TXSTAx

CSRC

TX9

TXEN

SYNC

BRGH

TRMT

TX9D

0000 -010

RCSTAx

SPEN

RX9

SREN

CREN

ADDEN

FERR

OERR

RX9D

0000 000x

SPBRGx Baud Rate Generator Register

0000 0000

Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used by the BRG.
Note:

Register names generically refer to both of the identically named registers for the two USART modules, where
`x' indicates the particular module. Bit names and RESET values are identical between modules.

2003 Microchip Technology Inc.

Advance Information

DS39609A-page 201

PIC18FXX20

TABLE 18-3:

BAUD RATES FOR SYNCHRONOUS MODE

BAUD

RATE

(Kbps)

OSC

= 40 MHz

33 MHz

25 MHz

20 MHz

KBAUD

ERROR

SPBRG

value

(decimal)

KBAUD

ERROR

SPBRG

value

(decimal)

KBAUD

ERROR

SPBRG

value

(decimal)

KBAUD

ERROR

SPBRG

value

(decimal)

0.3

1.2

2.4

9.6

19.2

76.8

76.92

+0.16

129

77.10

+0.39

106

77.16

+0.47

76.92

+0.16

96.15

+0.16

103

95.93

-0.07

96.15

+0.16

96.15

+0.16

300

303.03

+1.01

294.64

-1.79

297.62

-0.79

294.12

-1.96

500

485.30

-2.94

480.77

-3.85

500

HIGH

10000

8250

6250

5000

LOW

39.06

255

32.23

255

24.41

255

19.53

255

BAUD

RATE

(Kbps)

OSC

= 16 MHz

10 MHz

7.15909 MHz

5.0688 MHz

KBAUD

ERROR

SPBRG

value

(decimal)

KBAUD

ERROR

SPBRG

value

(decimal)

KBAUD

ERROR

SPBRG

value

(decimal)

KBAUD

ERROR

SPBRG

value

(decimal)

0.3

1.2

2.4

9.6 NA

9.62

+0.23

185

9.60

131

19.2

19.23

+0.16

207

19.23

+0.16

129

19.24

+0.23

19.20

76.8

76.92

+0.16

75.76

-1.36

77.82

+1.32

74.54

-2.94

95.24

-0.79

96.15

+0.16

94.20

-1.88

97.48

+1.54

300

307.70

+2.56

312.50

+4.17

298.35

-0.57

316.80

+5.60

500

447.44

-10.51

422.40

-15.52

HIGH

4000

2500

1789.80

1267.20

LOW

15.63

255

9.77

255

6.99

255

4.95

255

BAUD

RATE

(Kbps)

OSC

= 4 MHz

3.579545 MHz

1 MHz

32.768 kHz

KBAUD

ERROR

SPBRG

value

(decimal)

KBAUD

ERROR

SPBRG

value

(decimal)

KBAUD

ERROR

SPBRG

value

(decimal)

KBAUD

ERROR

SPBRG

value

(decimal)

0.3

0.30

+1.14

1.2

1.20

+0.16

207

1.17

-2.48

2.4

2.40

+0.16

103

2.73

+13.78

9.6

9.62

+0.16

103

9.62

+0.23

9.62

+0.16

8.20

-14.67

19.2

19.23

+0.16

19.04

-0.83

19.23

+0.16

76.8

76.92

+0.16

74.57

-2.90

83.33

+8.51

1000

+4.17

99.43

+3.57

83.33

-13.19

300

333.33

+11.11

298.30

-0.57

250

-16.67

500

447.44

-10.51

HIGH

1000

894.89

250

8.20

LOW

3.91

255

3.50

255

0.98

255

0.03

255

PIC18FXX20

DS39609A-page 202

Advance Information

2003 Microchip Technology Inc.

TABLE 18-4:

BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0)

BAUD

RATE

(Kbps)

OSC

= 40 MHz

33 MHz

25 MHz

20 MHz

KBAUD

ERROR

SPBRG

value

(decimal)

KBAUD

ERROR

SPBRG

value

(decimal)

KBAUD

ERROR

SPBRG

value

(decimal)

KBAUD

ERROR

SPBRG

value

(decimal)

0.3

1.2 NA

2.4 NA

2.40

-0.07

214

2.40

-0.15

162

2.40

+0.16

129

9.6 9.62

+0.16

9.55

-0.54

9.53

-0.76

9.47

-1.36

19.2

18.94

-1.36

19.10

-0.54

19.53

+1.73

19.53

+1.73

76.8

78.13

+1.73

73.66

-4.09

78.13

+1.73

78.13

+1.73

89.29

-6.99

103.13

+7.42

97.66

+1.73

104.17

+8.51

300

312.50

+4.17

257.81

-14.06

312.50

+4.17

500

625

+25.00

HIGH

625

515.63

390.63

312.50

LOW

2.44

255

2.01

255

1.53

255

1.22

255

BAUD

RATE

(Kbps)

OSC

= 16 MHz

10 MHz

7.15909 MHz

5.0688 MHz

KBAUD

ERROR

SPBRG

value

(decimal)

KBAUD

ERROR

SPBRG

value

(decimal)

KBAUD

ERROR

SPBRG

value

(decimal)

KBAUD

ERROR

SPBRG

value

(decimal)

0.3

NA -

1.2 1.20

+0.16

207

1.20

+0.16

129

1.20

+0.23

1.20

2.4 2.40

+0.16

103

2.40

+0.16

2.38

-0.83

2.40

9.6 9.62

+0.16

9.77

+1.73

9.32

-2.90

9.90

+3.13

19.2

19.23

+0.16

19.53

+1.73

18.64

-2.90

19.80

+3.13

76.8

83.33

+8.51

78.13

+1.73

111.86

+45.65

79.20

+3.13

83.33

-13.19

78.13

-18.62

300

250

-16.67

156.25

-47.92

500

HIGH

250

156.25

111.86

79.20

LOW

0.98

255

0.61

255

0.44

255

0.31

255

BAUD

RATE

(Kbps)

OSC

= 4 MHz

3.579545 MHz

1 MHz

32.768 kHz

KBAUD

ERROR

SPBRG

value

(decimal)

KBAUD

ERROR

SPBRG

value

(decimal)

KBAUD

ERROR

SPBRG

value

(decimal)

KBAUD

ERROR

SPBRG

value

(decimal)

0.3

0.30

-0.16

207

0.30

+0.23

185

0.30

+0.16

0.26

-14.67

1.2 1.20

+1.67

1.19

-0.83

1.20

+0.16

2.4 2.40

+1.67

2.43

+1.32

2.23

-6.99

9.6 8.93

-6.99

9.32

-2.90

7.81

-18.62

19.2

20.83

+8.51

18.64

-2.90

15.63

-18.62

76.8

62.50

-18.62

55.93

-27.17

300

500

HIGH

62.50

55.93

15.63

0.51

LOW

0.24

255

0.22

255

0.06

255

0.002

255

2003 Microchip Technology Inc.

Advance Information

DS39609A-page 203

PIC18FXX20

TABLE 18-5:

BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 1)

BAUD

RATE

(Kbps)

OSC

= 40 MHz

33 MHz

25 MHz

20 MHz

KBAUD

ERROR

SPBRG

value

(decimal)

KBAUD

ERROR

SPBRG

value

(decimal)

KBAUD

ERROR

SPBRG

value

(decimal)

KBAUD

ERROR

SPBRG

value

(decimal)

0.3

1.2

2.4

9.6

9.60

-0.07

214

9.59

-0.15

162

9.62

+0.16

129

19.2

19.23

+0.16

129

19.28

+0.39

106

19.30

+0.47

19.23

+0.16

76.8

75.76

-1.36

76.39

-0.54

78.13

+1.73

78.13

+1.73

96.15

+0.16

98.21

+2.31

97.66

+1.73

96.15

+0.16

300

312.50

+4.17

294.64

-1.79

312.50

+4.17

312.50

+4.17

500

515.63

+3.13

520.83

+4.17

416.67

-16.67

HIGH

2500

2062.50

1562.50

1250

LOW

9.77

255

8,06

255

6.10

255

4.88

255

BAUD

RATE

(Kbps)

OSC

= 16 MHz

10 MHz

7.15909 MHz

5.0688 MHz

KBAUD

ERROR

SPBRG

value

(decimal)

KBAUD

ERROR

SPBRG

value

(decimal)

KBAUD

ERROR

SPBRG

value

(decimal)

KBAUD

ERROR

SPBRG

value

(decimal)

0.3

1.2

2.4

2.41

+0.23

185

2.40

131

9.6

9.62

+0.16

103

9.62

+0.16

9.52

-0.83

9.60

19.2

19.23

+0.16

18.94

-1.36

19.45

+1.32

18.64

-2.94

76.8

76.92

+0.16

78.13

+1.73

74.57

-2.90

79.20

+3.13

100

+4.17

89.29

-6.99

89.49

-6.78

105.60

+10.00

300

333.33

+11.11

312.50

+4.17

447.44

+49.15

316.80

+5.60

500

625

+25.00

447.44

-10.51

HIGH

1000

625

447.44

316.80

LOW

3.91

255

2.44

255

1.75

255

1.24

255

BAUD

RATE

(Kbps)

OSC

= 4 MHz

3.579545 MHz

1 MHz

32.768 kHz

KBAUD

ERROR

SPBRG

value

(decimal)

KBAUD

ERROR

SPBRG

value

(decimal)

KBAUD

ERROR

SPBRG

value

(decimal)

KBAUD

ERROR

SPBRG

value

(decimal)

0.3

0.30

+0.16

207

0.29

-2.48

1.2

1.20

+0.16

207

1.20

+0.23

185

1.20

+0.16

1.02

-14.67

2.4

2.40

+0.16

103

2.41

+0.23

2.40

+0.16

2.05

-14.67

9.6

9.62

+0.16

9.73

+1.32

8.93

-6.99

19.2

19.23

+0.16

18.64

-2.90

20.83

+8.51

76.8

74.57

-2.90

62.50

-18.62

111.86

+16.52

300

223.72

-25.43

500

HIGH

250

55.93

62.50

2.05

LOW

0.98

255

0.22

255

0.24

255

0.008

255

PIC18FXX20

DS39609A-page 204

Advance Information

2003 Microchip Technology Inc.

18.2

USART Asynchronous Mode

In this mode, the USARTs use standard
non-return-to-zero (NRZ) format (one START bit, eight
or nine data bits and one STOP bit). The most common
data format is 8 bits. An on-chip dedicated 8-bit baud
rate generator can be used to derive standard baud
rate frequencies from the oscillator. The USART trans-
mits and receives the LSbit first. The USART's trans-
mitter and receiver are functionally independent, but
use the same data format and baud rate. The baud rate
generator produces a clock, either 16 or 64 times the
bit shift rate, depending on bit BRGH (TXSTAx<2>).
Parity is not supported by the hardware, but can be
implemented in software (and stored as the ninth data
bit). Asynchronous mode is stopped during SLEEP.
Asynchronous mode is selected by clearing bit SYNC
(TXSTAx<4>).
The USART Asynchronous module consists of the
following important elements:
� Baud Rate Generator
� Sampling Circuit
� Asynchronous Transmitter
� Asynchronous Receiver

18.2.1

USART ASYNCHRONOUS
TRANSMITTER

The USART transmitter block diagram is shown in
Figure 18-1. The heart of the transmitter is the Transmit
(serial) Shift Register (TSR). The shift register obtains
its data from the read/write transmit buffer, TXREGx.
The TXREGx register is loaded with data in software.
The TSR register is not loaded until the STOP bit has
been transmitted from the previous load. As soon as
the STOP bit is transmitted, the TSR is loaded with new
data from the TXREGx register (if available). Once the
TXREGx register transfers the data to the TSR register
(occurs in one T

), the TXREGx register is empty and

flag bit, TXx1IF (PIR1<4> for USART1, PIR3<4> for

USART2), is set. This interrupt can be enabled/dis-
abled by setting/clearing enable bit, TXxIE (PIE1<4>
for USART1, PIE<4> for USART2). Flag bit TXxIF will
be set, regardless of the state of enable bit TXxIE and
cannot be cleared in software. It will reset only when
new data is loaded into the TXREGx register. While flag
bit TXIF indicated the status of the TXREGx register,
another bit, TRMT (TXSTAx<1>), shows the status of
the TSR register. Status bit TRMT is a read only bit,
which is set when the TSR register is empty. No inter-
rupt logic is tied to this bit, so the user has to poll this
bit in order to determine if the TSR register is empty.

To set up an asynchronous transmission:
1.

Initialize the SPBRGx register for the appropri-
ate baud rate. If a high speed baud rate is
desired, set bit BRGH (Section 18.1).

Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.

If interrupts are desired, set enable bit TXxIE in
the appropriate PIE register.

If 9-bit transmission is desired, set transmit bit
TX9. Can be used as address/data bit.

Enable the transmission by setting bit TXEN,
which will also set bit TXxIF.

If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.

Load data to the TXREGx register (starts
transmission).

FIGURE 18-1:

USART TRANSMIT BLOCK DIAGRAM

Note 1: The TSR register is not mapped in data

memory, so it is not available to the user.

2: Flag bit TXIF is set when enable bit TXEN

is set.

Note:

TXIF is not cleared immediately upon load-
ing data into the transmit buffer TXREG.
The flag bit becomes valid in the second
instruction cycle following the load
instruction.

TXIF

TXIE

Interrupt

TXEN

Baud Rate CLK

SPBRG

Baud Rate Generator

TX9D

MSb

LSb

Data Bus

TXREG Register

TSR Register

(8)

TX9

TRMT

SPEN

TX pin

Pin Buffer

and Control

� � �

2003 Microchip Technology Inc.

Advance Information

DS39609A-page 205

PIC18FXX20

FIGURE 18-2:

ASYNCHRONOUS TRANSMISSION

FIGURE 18-3:

ASYNCHRONOUS TRANSMISSION (BACK TO BACK)

TABLE 18-6:

REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION

Word 1

STOP bit

Word 1

Transmit Shift Reg

START bit

bit 0

bit 1

bit 7/8

Write to TXREG

Word 1

BRG Output

(Shift Clock)

RC6/TX1/CK1 (pin)

TXIF bit

(Transmit Buffer

Reg. Empty Flag)

TRMT bit

(Transmit Shift

Reg. Empty Flag)

Transmit Shift Reg.

Write to TXREG

BRG Output

(Shift Clock)

RC6/TX1/CK1 (pin)

TXIF bit

(Interrupt Reg. Flag)

TRMT bit

(Transmit Shift

Reg. Empty Flag)

Word 1

Word 2

Word 1

Word 2

START bit

STOP bit

START bit

Transmit Shift Reg.

Word 1

Word 2

bit 0

bit 1

bit 7/8

bit 0

Note:

This timing diagram shows two consecutive transmissions.

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR,

BOR

Value on

all other

RESETS

INTCON

GIE/GIEH

PEIE/GIEL TMR0IE INT0IE

RBIE

TMR0IF

INT0IF

RBIF

0000 0000

PIR1

PSPIF

ADIF

RC1IF

TX1IF

SSPIF

CCP1IF

TMR2IF

TMR1IF

0000 0000

PIE1

PSPIE

ADIE

RC1IE

TX1IE

SSPIE

CCP1IE

TMR2IE

TMR1IE

0000 0000

IPR1

PSPIP

ADIP

RC1IP

TX1IP

SSPIP

CCP1IP

TMR2IP

TMR1IP

0111 1111

PIR3

RC2IF

TX2IF

TMR4IF

CCP5IF

CCP4IF

CCP3IF

--00 0000

PIE3

RC2IE

TX2IE

TMR4IE CCP5IE

CCP4IE

CCP3IE

--00 0000

IPR3

RC2IP

TX2IP

TMR4IP CCP5IP

CCP4IP

CCP3IP

--11 1111

RCSTAx

(1)

SPEN

RX9

SREN

CREN

ADDEN

FERR

OERR

RX9D

0000 000x

TXREGx

(1)

USART Transmit Register

0000 0000

TXSTAx

(1)

CSRC

TX9

TXEN

SYNC

BRGH

TRMT

TX9D

0000 -010

SPBRGx

(1)

Baud Rate Generator Register

0000 0000

Legend:

= unknown, - = unimplemented locations read as '0'. Shaded cells are not used for Asynchronous Transmission.

Note 1: Register names generically refer to both of the identically named registers for the two USART modules, where `x'

indicates the particular module. Bit names and RESET values are identical between modules.

PIC18FXX20

DS39609A-page 206

Advance Information

2003 Microchip Technology Inc.

18.2.2

USART ASYNCHRONOUS
RECEIVER

The USART receiver block diagram is shown in
Figure 18-4. The data is received on the pin
(RC7/RX1/DT1 or RG2/RX2/DT2) and drives the data
recovery block. The data recovery block is actually a
high speed shifter operating at 16 times the baud rate,
whereas the main receive serial shifter operates at the
bit rate or at F

OSC

. This mode would typically be used

in RS-232 systems.
To set up an Asynchronous Reception:
1.

Initialize the SPBRG register for the appropriate
baud rate. If a high speed baud rate is desired,
set bit BRGH (Section 18.1).

Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.

If interrupts are desired, set enable bit RCxIE.

If 9-bit reception is desired, set bit RX9.

Enable the reception by setting bit CREN.

Flag bit RCxIF will be set when reception is com-
plete and an interrupt will be generated if enable
bit RCxIE was set.

Read the RCSTAx register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.

Read the 8-bit received data by reading the
RCREG register.

If any error occurred, clear the error by clearing
enable bit CREN.

10. If using interrupts, ensure that the GIE and PEIE

bits in the INTCON register (INTCON<7:6>) are
set.

18.2.3

SETTING UP 9-BIT MODE WITH
ADDRESS DETECT

This mode would typically be used in RS-485 systems.
To set up an Asynchronous Reception with Address
Detect Enable:
1.

Initialize the SPBRGx register for the appropri-
ate baud rate. If a high speed baud rate is
required, set the BRGH bit.

Enable the asynchronous serial port by clearing
the SYNC bit and setting the SPEN bit.

If interrupts are required, set the RCEN bit and
select the desired priority level with the RCIP bit.

Set the RX9 bit to enable 9-bit reception.

Set the ADDEN bit to enable address detect.

Enable reception by setting the CREN bit.

The RCxIF bit will be set when reception is com-
plete. The interrupt will be Acknowledged if the
RCxIE and GIE bits are set.

Read the RCSTAx register to determine if any
error occurred during reception, as well as read
bit 9 of data (if applicable).

Read RCREGx to determine if the device is
being addressed.

10. If any error occurred, clear the CREN bit.
11. If the device has been addressed, clear the

ADDEN bit to allow all received data into the
receive buffer and interrupt the CPU.

FIGURE 18-4:

USART RECEIVE BLOCK DIAGRAM

x64 Baud Rate CLK

SPBRG

Baud Rate Generator

RX pin

Pin Buffer

and Control

SPEN

Data

Recovery

CREN

OERR

FERR

RSR Register

MSb

LSb

RX9D

RCREG Register

FIFO

Interrupt

RCIF

RCIE

Data Bus

� 64

� 16

STOP

START

(8)

RX9

� � �

2003 Microchip Technology Inc.

Advance Information

DS39609A-page 207

PIC18FXX20

FIGURE 18-5:

ASYNCHRONOUS RECEPTION

TABLE 18-7:

REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION

START

bit

bit7/8

bit1

bit0

bit7/8

bit0

STOP

bit

START

bit

START

bit

bit7/8 STOP

bit

RX (pin)

Reg

Rcv Buffer Reg

Rcv Shift

Read Rcv

Buffer Reg

RCREG

RCIF
(Interrupt Flag)

OERR bit

CREN

Word 1

RCREG

Word 2

RCREG

STOP

bit

Note:

This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR, BOR

Value on

all other

RESETS

INTCON

GIE/

GIEH

PEIE/

GIEL

TMR0IE

INT0IE

RBIE

TMR0IF

INT0IF

RBIF

0000 0000

PIR1

PSPIF

ADIF

RCIF

TXIF

SSPIF

CCP1IF TMR2IF TMR1IF

0000 0000

PIE1

PSPIE

ADIE

RCIE

TXIE

SSPIE

CCP1IE TMR2IE TMR1IE

0000 0000

IPR1

PSPIP

ADIP

RCIP

TXIP

SSPIP

CCP1IP TMR2IP TMR1IP

0111 1111

PIR3

RC2IF

TX2IF

TMR4IF CCP5IF CCP4IF

CCP3IF

--00 0000

PIE3

RC2IE

TX2IE

TMR4IE CCP5IE CCP4IE CCP3IE

--00 0000

IPR3

RC2IP

TX2IP

TMR4IP CCP5IP CCP4IP CCP3IP

--11 1111

RCSTAx

(1)

SPEN

RX9

SREN

CREN

ADDEN

FERR

OERR

RX9D

0000 000x

TXREGx

(1)

USART Receive Register

0000 0000

TXSTAx

(1)

CSRC

TX9

TXEN

SYNC

BRGH

TRMT

TX9D

0000 -010

SPBRGx

(1)

Baud Rate Generator Register

0000 0000

Legend:

= unknown, - = unimplemented locations read as '0'. Shaded cells are not used for Asynchronous Reception.

Note 1: Register names generically refer to both of the identically named registers for the two USART modules, where `x'

indicates the particular module. Bit names and RESET values are identical between modules.

PIC18FXX20

DS39609A-page 208

Advance Information

2003 Microchip Technology Inc.

18.3

USART Synchronous Master
Mode

In Synchronous Master mode, the data is transmitted in
a half-duplex manner (i.e., transmission and reception
do not occur at the same time). When transmitting data,
the reception is inhibited and vice versa. Synchronous
mode is entered by setting bit SYNC (TXSTAx<4>). In
addition, enable bit SPEN (RCSTAx<7>) is set in order
to configure the appropriate I/O pins to CK (clock) and
DT (data) lines, respectively. The Master mode indi-
cates that the processor transmits the master clock on
the CK line. The Master mode is entered by setting bit
CSRC (TXSTAx<7>).

18.3.1

USART SYNCHRONOUS MASTER
TRANSMISSION

The USART transmitter block diagram is shown in
Figure 18-1. The heart of the transmitter is the Transmit
(serial) Shift Register (TSR). The shift register obtains
its data from the read/write transmit buffer register,
TXREG. The TXREGx register is loaded with data in
software. The TSR register is not loaded until the last
bit has been transmitted from the previous load. As
soon as the last bit is transmitted, the TSR is loaded
with new data from the TXREGx (if available). Once the
TXREGx register transfers the data to the TSR register
(occurs in one T

CYCLE

), the TXREGx is empty and

interrupt bit TXxIF (PIR1<4> for USART1, PIR3<4> for
USART2) is set. The interrupt can be enabled/disabled
by setting/clearing enable bit TXxIE (PIE1<4> for

USART1, PIE3<4> for USART2). Flag bit TXxIF will be
set, regardless of the state of enable bit TXxIE, and
cannot be cleared in software. It will reset only when
new data is loaded into the TXREGx register. While flag
bit TXxIF indicates the status of the TXREGx register,
another bit TRMT (TXSTAx<1>) shows the status of the
TSR register. TRMT is a read only bit, which is set
when the TSR is empty. No interrupt logic is tied to this
bit, so the user has to poll this bit in order to determine
if the TSR register is empty. The TSR is not mapped in
data memory, so it is not available to the user.
To set up a Synchronous Master Transmission:
1.

Initialize the SPBRG register for the appropriate
baud rate (Section 18.1).

Enable the synchronous master serial port by
setting bits SYNC, SPEN, and CSRC.

If interrupts are desired, set enable bit TXxIE in
the appropriate PIE register.

If 9-bit transmission is desired, set bit TX9.

Enable the transmission by setting bit TXEN.

If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.

Start transmission by loading data to the
TXREGx register.

TABLE 18-8:

REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION

Note:

TXIF is not cleared immediately upon load-
ing data into the transmit buffer TXREG.
The flag bit becomes valid in the second
instruction cycle following the load
instruction.

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR,

BOR

Value on

all other

RESETS

INTCON

GIE/

GIEH

PEIE/

GIEL

TMR0IE

INT0IE

RBIE

TMR0IF

INT0IF

RBIF

0000 0000

PIR1

PSPIF

ADIF

RCIF

TXIF

SSPIF

CCP1IF

TMR2IF

TMR1IF

0000 0000

PIE1

PSPIE

ADIE

RCIE

TXIE

SSPIE

CCP1IE

TMR2IE

TMR1IE

0000 0000

IPR1

PSPIP

ADIP

RCIP

TXIP

SSPIP

CCP1IP

TMR2IP

TMR1IP

0111 1111

PIR3

RC2IF

TX2IF

TMR4IF

CCP5IF

CCP4IF

CCP3IF

--00 0000

PIE3

RC2IE

TX2IE

TMR4IE

CCP5IE

CCP4IE

CCP3IE

--00 0000

IPR3

RC2IP

TX2IP

TMR4IP

CCP5IP

CCP4IP

CCP3IP

--11 1111

RCSTAx

(1)

SPEN

RX9

SREN

CREN

ADDEN

FERR

OERR

RX9D

0000 000x

TXREGx

(1)

USART Transmit Register

0000 0000

TXSTAx

(1)

CSRC

TX9

TXEN

SYNC

BRGH

TRMT

TX9D

0000 -010

SPBRGx

(1)

Baud Rate Generator Register

0000 0000

Legend:

= unknown, - = unimplemented, read as '0'. Shaded cells are not used for Synchronous Master Transmission.

Note 1: Register names generically refer to both of the identically named registers for the two USART modules, where `x' indicates

the particular module. Bit names and RESET values are identical between modules.

PIC18FXX20

DS39609A-page 210

Advance Information

2003 Microchip Technology Inc.

18.3.2

USART SYNCHRONOUS MASTER
RECEPTION

Once Synchronous mode is selected, reception is
enabled by setting either enable bit SREN
(RCSTAx<5>), or enable bit CREN (RCSTAx<4>).
Data is sampled on the RXx pin (RC7/RX1/DT1 or
RG2/RX2/DT2) on the falling edge of the clock. If
enable bit SREN is set, only a single word is received.
If enable bit CREN is set, the reception is continuous
until CREN is cleared. If both bits are set, then CREN
takes precedence.
To set up a Synchronous Master Reception:
1.

Initialize the SPBRGx register for the appropriate
baud rate (Section 18.1).

Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.

Ensure bits CREN and SREN are clear.

If interrupts are desired, set enable bit RCxIE in
the appropriate PIE register.

If 9-bit reception is desired, set bit RX9.

If a single reception is required, set bit SREN.
For continuous reception, set bit CREN.

Interrupt flag bit RCxIF will be set when
reception is complete and an interrupt will be
generated if the enable bit RCxIE was set.

Read the RCSTAx register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.

Read the 8-bit received data by reading the
RCREGx register.

10. If any error occurred, clear the error by clearing

bit CREN.

11. If using interrupts, ensure that the GIE and PEIE

bits in the INTCON register (INTCON<7:6>) are
set.

TABLE 18-9:

REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION

FIGURE 18-8:

SYNCHRONOUS RECEPTION (MASTER MODE, SREN)

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR,

BOR

Value on

all other

RESETS

INTCON

GIE/GIEH PEIE/GIEL TMR0IE

INT0IE

RBIE

TMR0IF

INT0IF

RBIF

0000 0000

PIR1

PSPIF

ADIF

RC1IF

TX1IF

SSPIF

CCP1IF

TMR2IF

TMR1IF

0000 0000

PIE1

PSPIE

ADIE

RC1IE

TX1IE

SSPIE

CCP1IE

TMR2IE

TMR1IE

0000 0000

IPR1

PSPIP

ADIP

RC1IP

TX1IP

SSPIP

CCP1IP

TMR2IP

TMR1IP

0111 1111

PIR3

RC2IF

TX2IF

TMR4IF

CCP5IF

CCP4IF

CCP3IF

--00 0000

PIE3

RC2IE

TX2IE

TMR4IE

CCP5IE

CCP4IE

CCP3IE

--00 0000

IPR3

RC2IP

TX2IP

TMR4IP

CCP5IP

CCP4IP

CCP3IP

--11 1111

RCSTAx

(1)

SPEN

RX9

SREN

CREN

ADDEN

FERR

OERR

RX9D

0000 000x

TXREGx

(1)

USART Receive Register

0000 0000

TXSTAx

(1)

CSRC

TX9

TXEN

SYNC

BRGH

TRMT

TX9D

0000 -010

SPBRGx

(1)

Baud Rate Generator Register

0000 0000

Legend:

= unknown, - = unimplemented, read as '0'. Shaded cells are not used for Synchronous Master Reception.

Note 1: Register names generically refer to both of the identically named registers for the two USART modules, where `x' indicates

the particular module. Bit names and RESET values are identical between modules.

CREN bit

RC7/RX1/DT1 pin

RC6/TX1/CK1 pin

Write to

bit SREN

SREN bit

RCIF bit

(Interrupt)

Read

RXREG

Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

'0'

bit0

bit1

bit2

bit3

bit4

bit5

bit6

bit7

'0'

Q1 Q2 Q3 Q4

Note:

Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.

2003 Microchip Technology Inc.

Advance Information

DS39609A-page 211

PIC18FXX20

18.4

USART Synchronous Slave Mode

Synchronous Slave mode differs from the Master mode
in the fact that the shift clock is supplied externally at
the TXx pin (RC6/TX1/CK1 or RG1/TX2/CK2), instead
of being supplied internally in Master mode. TRISC<6>
must be set for this mode. This allows the device to
transfer or receive data while in SLEEP mode. Slave
mode is entered by clearing bit CSRC (TXSTAx<7>).

18.4.1

USART SYNCHRONOUS SLAVE
TRANSMIT

The operation of the Synchronous Master and Slave
modes are identical, except in the case of the SLEEP
mode.
If two words are written to the TXREG and then the
SLEEP

instruction is executed, the following will occur:

The first word will immediately transfer to the
TSR register and transmit.

The second word will remain in TXREG register.

Flag bit TXxIF will not be set.

When the first word has been shifted out of TSR,
the TXREGx register will transfer the second
word to the TSR and flag bit TXxIF will now be
set.

If enable bit TXxIE is set, the interrupt will wake
the chip from SLEEP. If the global interrupt is
enabled, the program will branch to the interrupt
vector.

To set up a Synchronous Slave Transmission:
1.

Enable the synchronous slave serial port by set-
ting bits SYNC and SPEN and clearing bit
CSRC.

Clear bits CREN and SREN.

If interrupts are desired, set enable bit TXxIE.

If 9-bit transmission is desired, set bit TX9.

Enable the transmission by setting enable bit
TXEN.

If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.

Start transmission by loading data to the
TXREGx register.

If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.

TABLE 18-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR, BOR

Value on

all other

RESETS

INTCON

GIE/

GIEH

PEIE/

GIEL

TMR0IE

INT0IE

RBIE

TMR0IF

INT0IF

RBIF

0000 0000

PIR1

PSPIF

ADIF

RC1IF

TX1IF

SSPIF

CCP1IF

TMR2IF

TMR1IF

0000 0000

PIE1

PSPIE

ADIE

RC1IE

TX1IE

SSPIE

CCP1IE

TMR2IE

TMR1IE

0000 0000

IPR1

PSPIP

ADIP

RC1IP

TX1IP

SSPIP

CCP1IP

TMR2IP

TMR1IP

0111 1111

PIR3

RC2IF

TX2IF

TMR4IF

CCP5IF

CCP4IF

CCP3IF

--00 0000

PIE3

RC2IE

TX2IE

TMR4IE

CCP5IE

CCP4IE

CCP3IE

--00 0000

IPR3

RC2IP

TX2IP

TMR4IP

CCP5IP

CCP4IP

CCP3IP

--11 1111

RCSTAx

(1)

SPEN

RX9

SREN

CREN

ADDEN

FERR

OERR

RX9D

0000 000x

TXREGx

(1)

USART Transmit Register

0000 0000

TXSTAx

(1)

CSRC

TX9

TXEN

SYNC

BRGH

TRMT

TX9D

0000 -010

SPBRGx

(1)

Baud Rate Generator Register

0000 0000

Legend:

= unknown, - = unimplemented, read as '0'. Shaded cells are not used for Synchronous Slave Transmission.

Note 1: Register names generically refer to both of the identically named registers for the two USART modules, where `x' indicates

the particular module. Bit names and RESET values are identical between modules.

PIC18FXX20

DS39609A-page 212

Advance Information

2003 Microchip Technology Inc.

18.4.2

USART SYNCHRONOUS SLAVE
RECEPTION

The operation of the Synchronous Master and Slave
modes is identical, except in the case of the SLEEP
mode and bit SREN, which is a "don't care" in Slave
mode.
If receive is enabled by setting bit CREN prior to the
SLEEP

instruction, then a word may be received during

SLEEP. On completely receiving the word, the RSR
register will transfer the data to the RCREG register,
and if enable bit RCIE bit is set, the interrupt generated
will wake the chip from SLEEP. If the global interrupt is
enabled, the program will branch to the interrupt vector.

To set up a Synchronous Slave Reception:
1.

Enable the synchronous master serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.

If interrupts are desired, set enable bit RCxIE.

If 9-bit reception is desired, set bit RX9.

To enable reception, set enable bit CREN.

Flag bit RCxIF will be set when reception is com-
plete. An interrupt will be generated if enable bit
RCxIE was set.

Read the RCSTAx register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.

Read the 8-bit received data by reading the
RCREGx register.

If any error occurred, clear the error by clearing
bit CREN.

If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.

TABLE 18-11: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR, BOR

Value on

all other

RESETS

INTCON

GIE/

GIEH

PEIE/

GIEL

TMR0IE

INT0IE

RBIE

TMR0IF

INT0IF

RBIF

0000 0000

PIR1

PSPIF

ADIF

RC1IF

TX1IF

SSPIF

CCP1IF

TMR2IF

TMR1IF

0000 0000

PIE1

PSPIE

ADIE

RC1IE

TX1IE

SSPIE

CCP1IE

TMR2IE

TMR1IE

0000 0000

IPR1

PSPIP

ADIP

RC1IP

TX1IP

SSPIP

CCP1IP

TMR2IP

TMR1IP

0111 1111

PIR3

RC2IF

TX2IF

TMR4IF

CCP5IF

CCP4IF

CCP3IF

--00 0000

PIE3

RC2IE

TX2IE

TMR4IE

CCP5IE

CCP4IE

CCP3IE

--00 0000

IPR3

RC2IP

TX2IP

TMR4IP

CCP5IP

CCP4IP

CCP3IP

--11 1111

RCSTAx

(1)

SPEN

RX9

SREN

CREN

ADDEN

FERR

OERR

RX9D

0000 000x

TXREGx

(1)

USART Receive Register

0000 0000

TXSTAx

(1)

CSRC

TX9

TXEN

SYNC

BRGH

TRMT

TX9D

0000 -010

SPBRGx

(1)

Baud Rate Generator Register

0000 0000

Legend:

= unknown, - = unimplemented, read as '0'. Shaded cells are not used for Synchronous Slave Reception.

Note 1: Register names generically refer to both of the identically named registers for the two USART modules, where `x'

indicates the particular module. Bit names and RESET values are identical between modules.

2003 Microchip Technology Inc.

Advance Information

DS39609A-page 213

PIC18FXX20

19.0 10-BIT ANALOG-TO-DIGITAL

CONVERTER (A/D) MODULE

The analog-to-digital (A/D) converter module has 12
inputs for the PIC18F6X20 devices and 16 for the
PIC18F8X20 devices. This module allows conversion
of an analog input signal to a corresponding 10-bit
digital number.

The module has five registers:
� A/D Result High Register (ADRESH)
� A/D Result Low Register (ADRESL)
� A/D Control Register 0 (ADCON0)
� A/D Control Register 1 ((ADCON1)
� A/D Control Register 2 ((ADCON2)
The ADCON0 register, shown in Register 19-1, con-
trols the operation of the A/D module. The ADCON1
register, shown in Register 19-2, configures the func-
tions of the port pins. The ADCON2 register, shown in
Register 19-3, configures the A/D clock source and
justification.

REGISTER 19-1:

ADCON0 REGISTER

U-0

R/W-0

CHS3

CHS2

CHS1

CHS0

GO/DONE

ADON

bit 7

bit 0

bit 7-6

Unimplemented: Read as '0'

bit 5-2

CHS3:CHS0: Analog Channel Select bits

0000

= Channel 0 (AN0)

0001

= Channel 1 (AN1)

0010

= Channel 2 (AN2)

0011

= Channel 3 (AN3)

0100

= Channel 4 (AN4)

0101

= Channel 5 (AN5)

0110

= Channel 6 (AN6)

0111

= Channel 7 (AN7)

1000

= Channel 8 (AN8)

1001

= Channel 9 (AN9)

1010

= Channel 10 (AN10)

1011

= Channel 11 (AN11)

1100

= Channel 12 (AN12)

(1)

1101

= Channel 13 (AN13)

(1)

1110

= Channel 14 (AN14)

(1)

1111

= Channel 15 (AN15)

(1)

Note 1: These channels are not available on the PIC18F6X20 (64-pin) devices.

bit 1

GO/DONE: A/D Conversion Status bit
When ADON = 1:
1

= A/D conversion in progress (setting this bit starts the A/D conversion, which is automatically

cleared by hardware when the A/D conversion is complete)

= A/D conversion not in progress

bit 0

ADON: A/D On bit
1

= A/D converter module is enabled

= A/D converter module is disabled

Legend:
R = Readable bit

W = Writable bit

U = Unimplemented bit, read as `0'

- n = Value at POR

`1' = Bit is set

`0' = Bit is cleared

x = Bit is unknown

PIC18FXX20

DS39609A-page 214

Advance Information

2003 Microchip Technology Inc.

REGISTER 19-2:

ADCON1 REGISTER

U-0

R/W-0

VCFG1

VCFG0

PCFG3

PCFG2

PCFG1

PCFG0

bit 7

bit 0

bit 7-6

Unimplemented: Read as '0'

bit 5-4

VCFG1:VCFG0: Voltage Reference Configuration bits:

bit 3-0

PCFG3:PCFG0: A/D Port Configuration Control bits:

Legend:
R = Readable bit

W = Writable bit

U = Unimplemented bit, read as `0'

- n = Value at POR

`1' = Bit is set

`0' = Bit is cleared

x = Bit is unknown

VCFG1
VCFG0

A/D V

REF

A/D V

REF

External V

REF

External V

REF

External V

REF

External V

REF

A = Analog input D = Digital I/O

Note:

Shaded cells indicate A/D channels available only on PIC18F8X20 devices.

PCFG3
PCFG0

AN1

AN9

AN8

AN7

AN6

AN5

AN4

AN3

AN2

AN1

AN0

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

2003 Microchip Technology Inc.

Advance Information

DS39609A-page 217

PIC18FXX20

The value in the ADRESH/ADRESL registers is not
modified for a Power-on Reset. The
ADRESH/ADRESL registers will contain unknown data
after a Power-on Reset.
After the A/D module has been configured as desired,
the selected channel must be acquired before the con-
version is started. The analog input channels must
have their corresponding TRIS bits selected as an
input. To determine acquisition time, see Section 19.1.
After this acquisition time has elapsed, the A/D
conversion can be started.

The following steps should be followed to do an A/D
conversion:
1.

Configure the A/D module:
� Configure analog pins, voltage reference and

digital I/O (ADCON1)

� Select A/D input channel (ADCON0)
� Select A/D conversion clock (ADCON2)
� Turn on A/D module (ADCON0)

Configure A/D interrupt (if desired):
� Clear ADIF bit
� Set ADIE bit
� Set GIE bit

Wait the required acquisition time.

Start conversion:
� Set GO/DONE bit (ADCON0 register)

Wait for A/D conversion to complete, by either:
� Polling for the GO/DONE bit to be cleared
OR
� Waiting for the A/D interrupt

Read A/D Result registers (ADRESH:ADRESL);
clear bit ADIF, if required.

For next conversion, go to step 1 or step 2, as
required. The A/D conversion time per bit is
defined as T

. A minimum wait of 2 T

required before next acquisition starts.

FIGURE 19-2:

ANALOG INPUT MODEL

AIN

ANx

5 pF

= 0.6V

I leakage

Sampling
Switch

HOLD

= 120 pF

Sampling Switch

5V
4V
3V
2V

5 6 7 8 9 10 11

( k

)

� 500 nA

Legend: C

LEAKAGE

SS
C

HOLD

= input capacitance
= threshold voltage
= leakage current at the pin due to

= interconnect resistance
= sampling switch
= sample/hold capacitance (from DAC)

various junctions

= sampling switch resistance

PIC18FXX20

DS39609A-page 218

Advance Information

2003 Microchip Technology Inc.

19.1

A/D Acquisition Requirements

For the A/D converter to meet its specified accuracy,
the charge holding capacitor (C

HOLD

) must be allowed

to fully charge to the input channel voltage level. The
analog input model is shown in Figure 19-2. The
source impedance (R

) and the internal sampling

switch (R

) impedance directly affect the time

required to charge the capacitor C

HOLD

. The sampling

switch (R

) impedance varies over the device voltage

). The source impedance affects the offset voltage

at the analog input (due to pin leakage current). The
maximum recommended impedance for analog
sources is 2.5 k

. After the analog input channel is

selected (changed), this acquisition must be done
before the conversion can be started.

To calculate the minimum acquisition time,
Equation 19-1 may be used. This equation assumes
that 1/2 LSb error is used (1024 steps for the A/D). The
1/2 LSb error is the maximum error allowed for the A/D
to meet its specified resolution.
Example 19-1 shows the calculation of the minimum
required acquisition time, T

ACQ

. This calculation is

based on the following application system
assumptions:
C

HOLD

120

2.5 k

Conversion Error

1/2 LSb

Rss = 7 k

Temperature

癈 (system max.)

HOLD

0V @ time = 0

EQUATION 19-1:

ACQUISITION TIME

EQUATION 19-2:

A/D MINIMUM CHARGING TIME

EXAMPLE 19-1:

CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME

Note:

When the conversion is started, the hold-
ing capacitor is disconnected from the
input pin.

ACQ

Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient

AMP

+ T

COFF

HOLD

= (V

REF

� (V

REF

/2048)) � (1 � e

(-Tc/C

HOLD

+ R

))

)

or
T

-(120 pF)(1 k

+ R

) ln(1/2047)

ACQ

AMP

+ T

COFF

Temperature coefficient is only required for temperatures > 25

癈.

ACQ

祍 + T

+ [(Temp � 25

癈)(0.05 祍/癈)]

-C

HOLD

+ R

) ln(1/2047)

-120 pF (1 k

+ 7 k + 2.5 k) ln(0.0004885)

-120 pF (10.5 k

) ln(0.0004885)

-1.26

祍 (-7.6241)

9.61

祍

ACQ

祍 + 9.61 祍 + [(50癈 � 25癈)(0.05 祍/癈)]

11.61

祍 + 1.25 祍

12.86

祍

2003 Microchip Technology Inc.

Advance Information

DS39609A-page 219

PIC18FXX20

19.2

Selecting the A/D Conversion
Clock

The A/D conversion time per bit is defined as T

. The

A/D conversion requires 12 T

per 10-bit conversion.

The source of the A/D conversion clock is software
selectable. There are seven possible options for T

� 2 T

OSC

� 4 T

OSC

� 8 T

OSC

� 16 T

OSC

� 32 T

OSC

� 64 T

OSC

� Internal RC oscillator

For correct A/D conversions, the A/D conversion clock
(T

) must be selected to ensure a minimum T

time

of 1.6

祍.

Table 19-1 shows the resultant T

times derived from

the device operating frequencies and the A/D clock
source selected.

19.3

Configuring Analog Port Pins

The ADCON1, TRISA, TRISF and TRISH registers
control the operation of the A/D port pins. The port pins
needed as analog inputs must have their correspond-
ing TRIS bits set (input). If the TRIS bit is cleared (out-
put), the digital output level (V

or V

) will be

converted.
The A/D operation is independent of the state of the
CHS3:CHS0 bits and the TRIS bits.

TABLE 19-1:

vs. DEVICE OPERATING FREQUENCIES

Note 1: When reading the port register, all pins

configured as analog input channels will
read as cleared (a low level). Pins config-
ured as digital inputs will convert an ana-
log input. Analog levels on a digitally
configured input will not affect the
conversion accuracy.

2: Analog levels on any pin defined as a dig-

ital input may cause the input buffer to
consume current out of the device's
specification limits.

AD Clock Source (T

)

Maximum Device Frequency

Operation

ADCS2:ADCS0

PIC18FXX20

PIC18LFXX20

2 T

OSC

000

1.25 MHz

666 kHz

4 T

OSC

100

2.50 MHz

1.33 MHz

8 T

OSC

001

5.00 MHz

2.67 MHz

16 T

OSC

101

10.0 MHz

5.33 MHz

32 T

OSC

010

20.0 MHz

10.67 MHz

64 T

OSC

110

40.0 MHz

21.33 MHz

x11

PIC18FXX20

DS39609A-page 220

Advance Information

2003 Microchip Technology Inc.

19.4

A/D Conversions

Figure 19-3 shows the operation of the A/D converter
after the GO bit has been set. Clearing the GO/DONE
bit during a conversion will abort the current conver-
sion. The A/D result register pair will NOT be updated
with the partially completed A/D conversion sample.
That is, the ADRESH:ADRESL registers will continue
to contain the value of the last completed conversion
(or the last value written to the ADRESH:ADRESL reg-
isters). After the A/D conversion is aborted, a 2 T

wait

is required before the next acquisition is started. After
this 2 T

wait, acquisition on the selected channel is

automatically started.

19.5

Use of the CCP2 Trigger

An A/D conversion can be started by the "special event
trigger" of the CCP2 module. This requires that the
CCP2M3:CCP2M0 bits (CCP2CON<3:0>) be pro-
grammed as 1011 and that the A/D module is enabled
(ADON bit is set). When the trigger occurs, the
GO/DONE bit will be set, starting the A/D conversion,
and the Timer1 (or Timer3) counter will be reset to zero.
Timer1 (or Timer3) is reset to automatically repeat the
A/D acquisition period with minimal software overhead
(moving ADRESH/ADRESL to the desired location).
The appropriate analog input channel must be selected
and the minimum acquisition done before the "special
event trigger" sets the GO/DONE bit (starts a
conversion).
If the A/D module is not enabled (ADON is cleared), the
"special event trigger" will be ignored by the A/D module,
but will still reset the Timer1 (or Timer3) counter.

FIGURE 19-3:

A/D CONVERSION T

CYCLES

Note:

The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.

1 T

2 T

3 T

4 T

5 T

6 T

7 T

Set GO bit

Holding capacitor is disconnected from analog input (typically 100 ns)

9 T

- T

Next Q4: ADRESH/ADRESL is loaded, GO bit is cleared,

ADIF bit is set, holding capacitor is connected to analog input.

Conversion Starts

2003 Microchip Technology Inc.

Advance Information

DS39609A-page 221

PIC18FXX20

TABLE 19-2:

SUMMARY OF A/D REGISTERS

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR, BOR

Value on

all other

RESETS

INTCON

GIE/

GIEH

PEIE/

GIEL

TMR0IE

INT0IE

RBIE

TMR0IF

INT0IF

RBIF

0000 0000

PIR1

PSPIF

ADIF

RCIF

TXIF

SSPIF

CCP1IF

TMR2IF

TMR1IF

0000 0000

PIE1

PSPIE

ADIE

RCIE

TXIE

SSPIE

CCP1IE

TMR2IE

TMR1IE

0000 0000

IPR1

PSPIP

ADIP

RCIP

TXIP

SSPIP

CCP1IP

TMR2IP

TMR1IP

0111 1111

PIR2

CMIF

BCLIF

LVDIF

TMR3IF

CCP2IF

-0-- 0000

PIE2

CMIE

BCLIE

LVDIE

TMR3IE

CCP2IE

-0-- 0000

IPR2

CMIP

BCLIP

LVDIP

TMR3IP

CCP2IP

-0-- 0000

ADRESH

A/D Result Register High Byte

xxxx xxxx

uuuu uuuu

ADRESL

A/D Result Register Low Byte

xxxx xxxx

uuuu uuuu

ADCON0

CHS3

CHS1

CHS0

GO/DONE

ADON

--00 0000

ADCON1

VCFG1

VCFG0

PCFG3

PCFG2

PCFG1

PCFG0

--00 0000

ADCON2

ADFM

ADCS2

ADCS1

ADCS0

0--- -000

PORTA

RA6

RA5

RA4

RA3

RA2

RA1

RA0

--0x 0000

--0u 0000

TRISA

PORTA Data Direction Register

--11 1111

PORTF

RF7

RF6

RF5

RF4

RF3

RF2

RF1

RF0

x000 0000

u000 0000

LATF

LATF7

LATF6

LATF5

LATF4

LATF3

LATF2

LATF1

LATF0

xxxx xxxx

uuuu uuuu

TRISF

PORTF Data Direction Control Register

1111 1111

PORTH

(1)

RH7

RH6

RH5

RH4

RH3

RH2

RH1

RH0

0000 xxxx

LATH

(1)

LATH7

LATH6

LATH5

LATH4

LATH3

LATH2

LATH1

LATH0

xxxx xxxx

uuuu uuuu

TRISH

(1)

PORTH Data Direction Control Register

1111 1111

Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used for A/D conversion.
Note 1: Only available on PIC18F8X20 devices.

PIC18FXX20

DS39609A-page 224

Advance Information

2003 Microchip Technology Inc.

20.1

Comparator Configuration

There are eight modes of operation for the compara-
tors. The CMCON register is used to select these
modes. Figure 20-1 shows the eight possible modes.
The TRISF register controls the data direction of the
comparator pins for each mode. If the Comparator

mode is changed, the comparator output level may not
be valid for the specified mode change delay shown in
Electrical Specifications (Section 26.0).

FIGURE 20-1:

COMPARATOR I/O OPERATING MODES

Note:

Comparator interrupts should be disabled
during a Comparator mode change.
Otherwise, a false interrupt may occur.

RF6/AN11

RF5/AN10

Off

(Read as '0')

Comparators Reset (POR Default Value)

CM2:CM0 = 000

RF4/AN9

RF3/AN8

Off

(Read as '0')

RF6/AN11

RF5/AN10

C1OUT

Two Independent Comparators

CM2:CM0 = 010

RF4/AN9

RF3/AN8

C2OUT

RF6/AN11

RF5/AN10

C1OUT

Two Common Reference Comparators

CM2:CM0 = 100

RF4/AN9

RF3/AN8

C2OUT

RF4/AN9

RF3/AN8

Off

(Read as '0')

One Independent Comparator with Output

CM2:CM0 = 001

RF6/AN11

RF5/AN10

C1OUT

RF6/AN11

RF5/AN10

Off

(Read as '0')

Comparators Off

CM2:CM0 = 111

RF4/AN9

RF3/AN8

Off

(Read as '0')

RF6/AN11

RF5/AN10

C1OUT

Four Inputs Multiplexed to Two Comparators

CM2:CM0 = 110

RF4/AN9

RF3/AN8

C2OUT

From V

REF

Module

CIS = 0
CIS = 1

RF6/AN11

RF5/AN10

C1OUT

Two Common Reference Comparators with Outputs

CM2:CM0 = 101

RF4/AN9

RF3/AN8

C2OUT

A = Analog Input, port reads zeros always D = Digital Input CIS (CMCON<3>) is the Comparator Input Switch

REF

RF6/AN11

RF5/AN10

C1OUT

Two Independent Comparators with Outputs

CM2:CM0 = 011

RF4/AN9

RF3/AN8

C2OUT

RF2/AN7/C1OUT

RF1/AN6/C2OUT

RF2/AN7/C1OUT

RF1/AN6/C2OUT

RF2/AN7/C1OUT

2003 Microchip Technology Inc.

Advance Information

DS39609A-page 225

PIC18FXX20

20.2

Comparator Operation

A single comparator is shown in Figure 20-2, along with
the relationship between the analog input levels and
the digital output. When the analog input at V

+ is less

than the analog input V

-, the output of the comparator

is a digital low level. When the analog input at V

+ is

greater than the analog input V

-, the output of the

comparator is a digital high level. The shaded areas of
the output of the comparator in Figure 20-2 represent
the uncertainty, due to input offsets and response time.

20.3

Comparator Reference

An external or internal reference signal may be used,
depending on the comparator operating mode. The
analog signal present at V

- is compared to the signal

at V

+, and the digital output of the comparator is

adjusted accordingly (Figure 20-2).

FIGURE 20-2:

SINGLE COMPARATOR

20.3.1

EXTERNAL REFERENCE SIGNAL

When external voltage references are used, the
comparator module can be configured to have the com-
parators operate from the same, or different reference
sources. However, threshold detector applications may
require the same reference. The reference signal must
be between V

and V

, and can be applied to either

pin of the comparator(s).

20.3.2

INTERNAL REFERENCE SIGNAL

The comparator module also allows the selection of an
internally generated voltage reference for the
comparators. Section 21.0 contains a detailed descrip-
tion of the Comparator Voltage Reference Module that
provides this signal. The internal reference signal is
used when comparators are in mode CM<2:0> = 110
(Figure 20-1). In this mode, the internal voltage
reference is applied to the V

+ pin of both comparators.

20.4

Comparator Response Time

Response time is the minimum time, after selecting a
new reference voltage or input source, before the
comparator output has a valid level. If the internal ref-
erence is changed, the maximum delay of the internal
voltage reference must be considered when using the
comparator outputs. Otherwise, the maximum delay of
the comparators should be used (Section 26.0).

20.5

Comparator Outputs

The comparator outputs are read through the CMCON
Register. These bits are read only. The comparator
outputs may also be directly output to the RF1 and RF2
I/O pins. When enabled, multiplexors in the output path
of the RF1 and RF2 pins will switch and the output of
each pin will be the unsynchronized output of the com-
parator. The uncertainty of each of the comparators is
related to the input offset voltage and the response time
given in the specifications. Figure 20-3 shows the
comparator output block diagram.
The TRISA bits will still function as an output
enable/disable for the RF1 and RF2 pins while in this
mode.
The polarity of the comparator outputs can be changed
using the C2INV and C1INV bits (CMCON<4:5>).

�

Output

IN�

IN+

Output

Note 1: When reading the PORT register, all pins

configured as analog inputs will read as a
`0'. Pins configured as digital inputs will
convert an analog input, according to the
Schmitt Trigger input specification.

2: Analog levels on any pin defined as a dig-

ital input, may cause the input buffer to
consume more current than is specified.

2003 Microchip Technology Inc.

Advance Information

DS39609A-page 227

PIC18FXX20

20.7

Comparator Operation During
SLEEP

When a comparator is active and the device is placed
in SLEEP mode, the comparator remains active and
the interrupt is functional, if enabled. This interrupt will
wake-up the device from SLEEP mode, when enabled.
While the comparator is powered up, higher SLEEP
currents than shown in the power-down current
specification will occur. Each operational comparator
will consume additional current, as shown in the com-
parator specifications. To minimize power consumption
while in SLEEP mode, turn off the comparators,
CM<2:0> = 111, before entering SLEEP. If the device
wakes up from SLEEP, the contents of the CMCON
register are not affected.

20.8

Effects of a RESET

A device RESET forces the CMCON register to its
RESET state, causing the comparator module to be in
the comparator RESET mode, CM<2:0> = 000. This
ensures that all potential inputs are analog inputs.
Device current is minimized when analog inputs are
present at RESET time. The comparators will be
powered down during the RESET interval.

20.9

Analog Input Connection
Considerations

A simplified circuit for an analog input is shown in
Figure 20-4. Since the analog pins are connected to a
digital output, they have reverse biased diodes to V

and V

. The analog input, therefore, must be between

and V

. If the input voltage deviates from this

range by more than 0.6V in either direction, one of the
diodes is forward biased and a latchup condition may
occur. A maximum source impedance of 10 k

is rec-

ommended for the analog sources. Any external com-
ponent connected to an analog input pin, such as a
capacitor or a Zener diode, should have very little
leakage current.

FIGURE 20-4:

COMPARATOR ANALOG INPUT MODEL

< 10k

5 pF

= 0.6V

LEAKAGE

�500 nA

Legend:

= Input Capacitance

= Threshold

Voltage

LEAKAGE

= Leakage Current at the pin due to various junctions

= Interconnect Resistance

= Source

Impedance

= Analog

Voltage

Comparator
Input

2003 Microchip Technology Inc.

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DS39609A-page 229

PIC18FXX20

21.0 COMPARATOR VOLTAGE

REFERENCE MODULE

The Comparator Voltage Reference is a 16-tap resistor
ladder network that provides a selectable voltage refer-
ence. The resistor ladder is segmented to provide two
ranges of CV

REF

values and has a power-down func-

tion to conserve power when the reference is not being
used. The CVRCON register controls the operation of
the reference as shown in Register 21-1. The block
diagram is given in Figure 21-1.
The comparator reference supply voltage can come
from either V

or V

, or the external V

REF

+ and

REF

- that are multiplexed with RA3 and RA2. The

comparator reference supply voltage is controlled by
the CVRSS bit.

21.1

Configuring the Comparator
Voltage Reference

The Comparator Voltage Reference can output 16 dis-
tinct voltage levels for each range. The equations used
to calculate the output of the Comparator Voltage
Reference are as follows:

If CVRR = 1:
CV

REF

= (CVR<3:0>/24) x CV

RSRC

If CVRR = 0:
CV

REF

= (CV

x 1/4) + (CVR<3:0>/32) x CV

RSRC

The settling time of the Comparator Voltage Reference
must be considered when changing the CV

REF

output

(Section 26.0).

REGISTER 21-1:

CVRCON REGISTER

Note:

In order to select external V

REF

+ and V

REF

supply voltages, the Voltage Reference
Configuration bits (VCFG1:VCFG0) of the
ADCON1 register must be set appropriately.

R/W-0

CVREN

CVROE

CVRR

CVRSS

CVR3

CVR2

CVR1

CVR0

bit 7

bit 0

bit 7

CVREN: Comparator Voltage Reference Enable bit

= CV

REF

circuit powered on

= CV

REF

circuit powered down

bit 6

CVROE: Comparator V

REF

Output Enable bit

(1)

= CV

REF

voltage level is also output on the RF5/AN10/CV

REF

= CV

REF

voltage is disconnected from the RF5/AN10/CV

REF

bit 5

CVRR: Comparator V

REF

Range Selection bit

= 0.00 CV

RSRC

to 0.75 CV

RSRC

, with CV

RSRC

/24 step size

= 0.25 CV

RSRC

to 0.75 CV

RSRC

, with CV

RSRC

/32 step size

bit 4

CVRSS: Comparator V

REF

Source Selection bit

(2)

= Comparator reference source CV

RSRC

= V

REF

+ � V

REF

= Comparator reference source CV

RSRC

= V

� V

bit 3-0

CVR3:CVR0: Comparator V

REF

Value Selection bits (0

VR3:VR0 15)

When CVRR = 1:
CV

REF

= (CVR<3:0>/ 24)

� (CV

RSRC

)

When CVRR = 0:
CV

REF

= 1/4

� (CV

RSRC

) + (CVR3:CVR0/ 32)

� (CV

RSRC

)

Note 1: If enabled for output, RF5 must also be configured as an input by setting TRISF<5>

to `1'.

2: In order to select external V

REF

+ and V

REF

- supply voltages, the Voltage Refer-

ence Configuration bits (VCFG1:VCFG0) of the ADCON1 register must be set
appropriately.

Legend:
R = Readable bit

W = Writable bit

U = Unimplemented bit, read as `0'

- n = Value at POR

`1' = Bit is set

`0' = Bit is cleared

x = Bit is unknown

PIC18FXX20

DS39609A-page 230

Advance Information

2003 Microchip Technology Inc.

FIGURE 21-1:

VOLTAGE REFERENCE BLOCK DIAGRAM

21.2

Voltage Reference Accuracy/Error

The full range of voltage reference cannot be realized
due to the construction of the module. The transistors
on the top and bottom of the resistor ladder network
(Figure 21-1) keep CV

REF

from approaching the refer-

ence source rails. The voltage reference is derived
from the reference source; therefore, the CV

REF

output

changes with fluctuations in that source. The tested
absolute accuracy of the voltage reference can be
found in Section 26.0.

21.3

Operation During SLEEP

When the device wakes up from SLEEP through an
interrupt or a Watchdog Timer time-out, the contents of
the CVRCON register are not affected. To minimize
current consumption in SLEEP mode, the voltage
reference should be disabled.

21.4

Effects of a RESET

A device RESET disables the voltage reference by
clearing bit CVREN (CVRCON<7>). This RESET also
disconnects the reference from the RA2 pin by clearing
bit CVROE (CVRCON<6>) and selects the high volt-
age range by clearing bit CVRR (CVRCON<5>). The
VRSS value select bits, CVRCON<3:0>, are also
cleared.

21.5

Connection Considerations

The voltage reference module operates independently
of the comparator module. The output of the reference
generator may be connected to the RF5 pin if the
TRISF<5> bit is set and the CVROE bit is set. Enabling
the voltage reference output onto the RF5 pin, with an
input signal present, will increase current consumption.
Connecting RF5 as a digital output with VRSS enabled
will also increase current consumption.
The RF5 pin can be used as a simple D/A output with
limited drive capability. Due to the limited current drive
capability, a buffer must be used on the voltage refer-
ence output for external connections to V

REF

Figure 21-2 shows an example buffering technique.

Note: R is defined in Section 26.0.

CVRR

CVR3

CVR0

(From CVRCON<3:0>)

16-1 Analog Mux

CVREN

REF

16 Stages

CVRSS = 0

REF

CVRSS = 0

CVRSS = 1

REF

CVRSS = 1

2003 Microchip Technology Inc.

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DS39609A-page 233

PIC18FXX20

22.0 LOW VOLTAGE DETECT

In many applications, the ability to determine if the
device voltage (V

) is below a specified voltage level

is a desirable feature. A window of operation for the
application can be created, where the application soft-
ware can do "housekeeping tasks" before the device
voltage exits the valid operating range. This can be
done using the Low Voltage Detect module.
This module is a software programmable circuitry,
where a device voltage trip point can be specified.
When the voltage of the device becomes lower then the
specified point, an interrupt flag is set. If the interrupt is
enabled, the program execution will branch to the inter-
rupt vector address and the software can then respond
to that interrupt source.

The Low Voltage Detect circuitry is completely under
software control. This allows the circuitry to be "turned
off" by the software, which minimizes the current
consumption for the device.
Figure 22-1 shows a possible application voltage curve
(typically for batteries). Over time, the device voltage
decreases. When the device voltage equals voltage V

the LVD logic generates an interrupt. This occurs at
time T

. The application software then has the time,

until the device voltage is no longer in valid operating
range, to shut-down the system. Voltage point V

is the

minimum valid operating voltage specification. This
occurs at time T

. The difference T

� T

is the total

time for shutdown.

FIGURE 22-1:

TYPICAL LOW VOLTAGE DETECT APPLICATION

The block diagram for the LVD module is shown in
Figure 22-2. A comparator uses an internally gener-
ated reference voltage as the set point. When the
selected tap output of the device voltage crosses the
set point (is lower than), the LVDIF bit is set.
Each node in the resistor divider represents a "trip
point" voltage. The "trip point" voltage is the minimum
supply voltage level at which the device can operate
before the LVD module asserts an interrupt. When the

supply voltage is equal to the trip point, the voltage
tapped off of the resistor array is equal to the 1.2V
internal reference voltage generated by the voltage ref-
erence module. The comparator then generates an
interrupt signal setting the LVDIF bit. This voltage is
software programmable to any one of 16 values (see
Figure 22-2). The trip point is selected by programming
the LVDL3:LVDL0 bits (LVDCON<3:0>).

Time

l
t
a
g

= LVD trip point

= Minimum valid device

operating voltage

Legend:

2003 Microchip Technology Inc.

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DS39609A-page 239

PIC18FXX20

23.0 SPECIAL FEATURES OF THE

CPU

There are several features intended to maximize sys-
tem reliability, minimize cost through elimination of
external components, provide power saving operating
modes and offer code protection. These are:
� Osc Selection
� RESET

- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)

� Interrupts
� Watchdog Timer (WDT)
� SLEEP
� Code Protection
� ID Locations
� In-Circuit Serial Programming
All PIC18FXX20 devices have a Watchdog Timer,
which is permanently enabled via the configuration bits,
or software controlled. It runs off its own RC oscillator
for added reliability. There are two timers that offer nec-
essary delays on power-up. One is the Oscillator
Start-up Timer (OST), intended to keep the chip in
RESET until the crystal oscillator is stable. The other is
the Power-up Timer (PWRT), which provides a fixed
delay on power-up only, designed to keep the part in
RESET while the power supply stabilizes. With these
two timers on-chip, most applications need no external
RESET circuitry.
SLEEP mode is designed to offer a very low current
power-down mode. The user can wake-up from SLEEP
through external RESET, Watchdog Timer Wake-up, or
through an interrupt. Several oscillator options are also
made available to allow the part to fit the application.
The RC oscillator option saves system cost, while the
LP crystal option saves power. A set of configuration
bits are used to select various options.

23.1

Configuration Bits

The configuration bits can be programmed (read as '0'),
or left unprogrammed (read as '1'), to select various
device configurations. These bits are mapped, starting
at program memory location 300000h.
The user will note that address 300000h is beyond the
user program memory space. In fact, it belongs to the
configuration memory space (300000h through
3FFFFFh), which can only be accessed using Table
Reads and Table Writes.
Programming the configuration registers is done in a
manner similar to programming the FLASH memory.
The EECON1 register WR bit starts a self-timed write
to the configuration register. In normal Operation mode,
a TBLWT instruction with the TBLPTR pointed to the
configuration register sets up the address and the data
for the configuration register write. Setting the WR bit
starts a long write to the configuration register. The con-
figuration registers are written a byte at a time. To write
or erase a configuration cell, a TBLWT instruction can
write a `1' or a `0' into the cell.

PIC18FXX20

DS39609A-page 240

Advance Information

2003 Microchip Technology Inc.

TABLE 23-1:

CONFIGURATION BITS AND DEVICE IDS

File Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default/

Unprogrammed

Value

300001h

CONFIG1H

OSCSEN

FOSC2

FOSC1

FOSC0

--1- -111

300002h

CONFIG2L

BORV1

BORV0

BODEN

PWRTEN

---- 1111

300003h

CONFIG2H

WDTPS2 WDTPS1

WDTPS0

WDTEN

---- 1111

300004h

(1)

CONFIG3L

WAIT

PM1

PM0

1--- --11

300005h

CONFIG3H

T1OSCMX

(3)

CCP2MX

---- --11

300006h

CONFIG4L DEBUG

LVP

STVREN

1--- -1-1

300008h

CONFIG5L

CP7

(2)

CP6

(2)

CP5

(2)

CP4

(2)

CP3

CP2

CP1

CP0

1111 1111

300009h

CONFIG5H

CPD

CPB

11-- ----

30000Ah CONFIG6L WRT7

(2)

WRT6

(2)

WRT5

(2)

WRT4

(2)

WRT3

WRT2

WRT1

WRT0

1111 1111

30000Bh CONFIG6H

WRTD

WRTB

WRTC

111- ----

30000Ch CONFIG7L EBTR7

(2)

EBTR6

(2)

EBTR5

(2)

EBTR4

(2)

EBTR3

EBTR2

EBTR1

EBTR0

1111 1111

30000Dh CONFIG7H

EBTRB

-1-- ----

3FFFFEh DEVID1

DEV2

DEV1

DEV0

REV4

REV3

REV2

REV1

REV0

(4)

3FFFFFh DEVID2

DEV10

DEV9

DEV8

DEV7

DEV6

DEV5

DEV4

DEV3

0000 0110

Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition.

Shaded cells are unimplemented, read as `0'.

Note 1: Unimplemented in PIC18F6X20 devices; maintain this bit set.

2: Unimplemented in PIC18FX520 and PIC18FX620 devices; maintain this bit set.
3: Unimplemented in PIC18FX620 and PIC18FX720 devices; maintain this bit set.
4: See Register 23-13 for DEVID1 values.

2003 Microchip Technology Inc.

Advance Information

DS39609A-page 241

PIC18FXX20

REGISTER 23-1:

CONFIG1H: CONFIGURATION REGISTER 1 HIGH (BYTE ADDRESS 300001h)

REGISTER 23-2:

CONFIG2L: CONFIGURATION REGISTER 2 LOW (BYTE ADDRESS 300002h)

U-0

R/P-1

U-0

R/P-1

OSCSEN

FOSC2

FOSC1

FOSC0

bit 7

bit 0

bit 7-6

Unimplemented: Read as `0'

bit 5

OSCSEN: Oscillator System Clock Switch Enable bit

= Oscillator system clock switch option is disabled (main oscillator is source)

= Timer1 Oscillator system clock switch option is enabled (oscillator switching is enabled)

bit 4-3

Unimplemented: Read as `0'

bit 2-0

FOSC2:FOSC0: Oscillator Selection bits

111

= RC oscillator w/ OSC2 configured as RA6

110

= HS oscillator with PLL enabled; clock frequency = (4 x F

OSC

)

101

= EC oscillator w/ OSC2 configured as RA6

100

= EC oscillator w/ OSC2 configured as divide-by-4 clock output

011

= RC oscillator w/ OSC2 configured as divide-by-4 clock output

010

= HS oscillator

001

= XT oscillator

000

= LP oscillator

Legend:
R = Readable bit

P = Programmable bit

U = Unimplemented bit, read as `0'

- n = Value when device is unprogrammed

u = Unchanged from programmed state

U-0

R/P-1

BORV1

BORV0

BOREN

PWRTEN

bit 7

bit 0

bit 7-4

Unimplemented: Read as `0'

bit 3-2

BORV1:BORV0: Brown-out Reset Voltage bits

= V

BOR

set to 2.5V

= V

BOR

set to 2.7V

= V

BOR

set to 4.2V

= V

BOR

set to 4.5V

bit 1

BOREN: Brown-out Reset Enable bit

= Brown-out Reset enabled

= Brown-out Reset disabled

bit 0

PWRTEN: Power-up Timer Enable bit

= PWRT disabled

= PWRT enabled

Legend:
R = Readable bit

P = Programmable bit

U = Unimplemented bit, read as `0'

- n = Value when device is unprogrammed

u = Unchanged from programmed state

2003 Microchip Technology Inc.

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DS39609A-page 243

PIC18FXX20

REGISTER 23-5:

CONFIG3H: CONFIGURATION REGISTER 3 HIGH (BYTE ADDRESS 300005h)

REGISTER 23-6:

CONFIG4L: CONFIGURATION REGISTER 4 LOW (BYTE ADDRESS 300006h)

U-0

R/P-1

T1OSCMX

(1)

CCP2MX

bit 7

bit 0

bit 7-2

Unimplemented: Read as `0'

bit 1

T1OSCMX: Timer1 Oscillator Mode bit

(1)

= Standard (legacy) Timer1 oscillator operation

= Low power Timer1 operation when microcontroller is in SLEEP mode

bit 0

CCP2MX: CCP2 Mux bit
In Microcontroller mode:

= CCP2 input/output is multiplexed with RC1

= CCP2 input/output is multiplexed with RE7

In Microprocessor, Microprocessor with Boot Block and Extended Microcontroller modes
(PIC18F8X20 devices only):

= CCP2 input/output is multiplexed with RC1

= CCP2 input/output is multiplexed with RB3

Note 1: Unimplemented in PIC18FX620 and PIC18FX720 devices; maintain this bit set.

Legend:
R = Readable bit

P = Programmable bit

U = Unimplemented bit, read as `0'

- n = Value when device is unprogrammed

u = Unchanged from programmed state

R/P-1

U-0

R/P-1

U-0

R/P-1

DEBUG

LVP

STVREN

bit 7

bit 0

bit 7

DEBUG: Background Debugger Enable bit

= Background Debugger disabled. RB6 and RB7 configured as general purpose I/O pins.

= Background Debugger enabled. RB6 and RB7 are dedicated to In-Circuit Debug.

bit 6-3

Unimplemented: Read as `0'

bit 2

LVP: Low Voltage ICSP Enable bit

= Low Voltage ICSP enabled

= Low Voltage ICSP disabled

bit 1

Unimplemented: Read as `0'

bit 0

STVREN: Stack Full/Underflow Reset Enable bit

= Stack Full/Underflow will cause RESET

= Stack Full/Underflow will not cause RESET

Legend:
R = Readable bit

P = Programmable bit

U = Unimplemented bit, read as `0'

- n = Value when device is unprogrammed

u = Unchanged from programmed state

PIC18FXX20

DS39609A-page 244

Advance Information

2003 Microchip Technology Inc.

REGISTER 23-7:

CONFIG5L: CONFIGURATION REGISTER 5 LOW (BYTE ADDRESS 300008h)

R/P-1

CP7

(1)

CP6

(1)

CP5

(1)

CP4

(1)

CP3

CP2

CP1

CP0

bit 7

bit 0

bit 7

CP7: Code Protection bit

(1)

= Block 7 (01C000-01FFFFh) not code protected

= Block 7 (01C000-01FFFFh) code protected

bit 6

CP6: Code Protection bit

(1)

= Block 6 (018000-01BFFFh) not code protected

= Block 6 (018000-01BFFFh) code protected

bit 5

CP5: Code Protection bit

(1)

= Block 5 (014000-017FFFh) not code protected

= Block 5 (014000-017FFFh) code protected

bit 4

CP4: Code Protection bit

(1)

= Block 4 (010000-013FFFh) not code protected

= Block 4 (010000-013FFFh) code protected

bit 3

CP3: Code Protection bit
For PIC18FX520 devices:
1

= Block 3 (006000-007FFFh) not code protected

= Block 3 (006000-007FFFh) code protected

For PIC18FX620 and PIC18FX720 devices:
1

= Block 3 (00C000-00FFFFh) not code protected

= Block 3 (00C000-00FFFFh) code protected

bit 2

CP2: Code Protection bit
For PIC18FX520 devices:
1

= Block 2 (004000-005FFFh) not code protected

= Block 2 (004000-005FFFh) code protected

For PIC18FX620 and PIC18FX720 devices:
1

= Block 2 (008000-00BFFFh) not code protected

= Block 2 (008000-00BFFFh) code protected

bit 1

CP1: Code Protection bit
For PIC18FX520 devices:
1

= Block 1 (002000-003FFFh) not code protected

= Block 1 (002000-003FFFh) code protected

For PIC18FX620 and PIC18FX720 devices:
1

= Block 1 (004000-007FFFh) not code protected

= Block 1 (004000-007FFFh) code protected

bit 0

CP0: Code Protection bit
For PIC18FX520 devices:
1

= Block 0 (000800-001FFFh) not code protected

= Block 0 (000800-001FFFh) code protected

For PIC18FX620 and PIC18FX720 devices:
1

= Block 0 (000200-003FFFh) not code protected

= Block 0 (000200-003FFFh) code protected

Note 1: Unimplemented in PIC18FX520 and PIC18FX620 devices; maintain this bit set.

Legend:
R = Readable bit

P = Programmable bit

U = Unimplemented bit, read as `0'

- n = Value when device is unprogrammed

u = Unchanged from programmed state

PIC18FXX20

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2003 Microchip Technology Inc.

REGISTER 23-9:

CONFIG6L: CONFIGURATION REGISTER 6 LOW (BYTE ADDRESS 30000Ah)

R/P-1

WRT7

(1)

WRT6

(1)

WRT5

(1)

WRT4

(1)

WRT3

WRT2

WRT1

WRT0

bit 7

bit 0

bit 7

WR7: Write Protection bit

(1)

= Block 7 (01C000-01FFFFh) not write protected

= Block 7 (01C000-01FFFFh) write protected

bit 6

WR6: Write Protection bit

(1)

= Block 6 (018000-01BFFFh) not write protected

= Block 6 (018000-01BFFFh) write protected

bit 5

WR5: Write Protection bit

(1)

= Block 5 (014000-017FFFh) not write protected

= Block 5 (014000-017FFFh) write protected

bit 4

WR4: Write Protection bit

(1)

= Block 4 (010000-013FFFh) not write protected

= Block 4 (010000-013FFFh) write protected

bit 3

WR3: Write Protection bit
For PIC18FX520 devices:
1

= Block 3 (006000-007FFFh) not write protected

= Block 3 (006000-007FFFh) write protected

For PIC18FX620 and PIC18FX720 devices:
1

= Block 3 (00C000-00FFFFh) not write protected

= Block 3 (00C000-00FFFFh) write protected

bit 2

WR2: Write Protection bit
For PIC18FX520 devices:
1

= Block 2 (004000-005FFFh) not write protected

= Block 2 (004000-005FFFh) write protected

For PIC18FX620 and PIC18FX720 devices:
1

= Block 2 (008000-00BFFFh) not write protected

= Block 2 (008000-00BFFFh) write protected

bit 1

WR1: Write Protection bit
For PIC18FX520 devices:
1

= Block 1 (002000-003FFFh) not write protected

= Block 1 (002000-003FFFh) write protected

For PIC18FX620 and PIC18FX720 devices:
1

= Block 1 (004000-007FFFh) not write protected

= Block 1 (004000-007FFFh) write protected

bit 0

WR0: Write Protection bit
For PIC18FX520 devices:
1

= Block 0 (000800-001FFFh) not write protected

= Block 0 (000800-001FFFh) write protected

For PIC18FX620 and PIC18FX720 devices:
1

= Block 0 (000200-003FFFh) not write protected

= Block 0 (000200-003FFFh) write protected

Note 1: Unimplemented in PIC18FX520 and PIC18FX620 devices; maintain this bit set.

Legend:
R = Readable bit

P = Programmable bit

U = Unimplemented bit, read as `0'

- n = Value when device is unprogrammed

u = Unchanged from programmed state

PIC18FXX20

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2003 Microchip Technology Inc.

REGISTER 23-11: CONFIG7L: CONFIGURATION REGISTER 7 LOW (BYTE ADDRESS 30000Ch)

R/P-1

EBTR7

(1)

EBTR6

(1)

EBTR5

(1)

EBTR4

(1)

EBTR3

EBTR2

EBTR1

EBTR0

bit 7

bit 0

bit 7

EBTR7: Table Read Protection bit

(1)

= Block 3 (01C000-01FFFFh) not protected from Table Reads executed in other blocks

= Block 3 (01C000-01FFFFh) protected from Table Reads executed in other blocks

bit 6

EBTR6: Table Read Protection bit

(1)

= Block 2 (018000-01BFFFh) not protected from Table Reads executed in other blocks

= Block 2 (018000-01BFFFh) protected from Table Reads executed in other blocks

bit 5

EBTR5: Table Read Protection bit

(1)

= Block 1 (014000-017FFFh) not protected from Table Reads executed in other blocks

= Block 1 (014000-017FFFh) protected from Table Reads executed in other blocks

bit 4

EBTR4: Table Read Protection bit

(1)

= Block 0 (010000-013FFFh) not protected from Table Reads executed in other blocks

= Block 0 (010000-013FFFh) protected from Table Reads executed in other blocks

bit 3

EBTR3: Table Read Protection bit
For PIC18FX520 devices:
1

= Block 3 (006000-007FFFh) not protected from Table Reads executed in other blocks

= Block 3 (006000-007FFFh) protected from Table Reads executed in other blocks

For PIC18FX620 and PIC18FX720 devices:
1

= Block 3 (00C000-00FFFFh) not protected from Table Reads executed in other blocks

= Block 3 (00C000-00FFFFh) protected from Table Reads executed in other blocks

bit 2

EBTR2: Table Read Protection bit
For PIC18FX520 devices:
1

= Block 2 (004000-005FFFh) not protected from Table Reads executed in other blocks

= Block 2 (004000-005FFFh) protected from Table Reads executed in other blocks

For PIC18FX620 and PIC18FX720 devices:
1

= Block 2 (008000-00BFFFh) not protected from Table Reads executed in other blocks

= Block 2 (008000-00BFFFh) protected from Table Reads executed in other blocks

bit 1

EBTR1: Table Read Protection bit
For PIC18FX520 devices:
1

= Block 1 (002000-003FFFh) not protected from Table Reads executed in other blocks

= Block 1 (002000-003FFFh) protected from Table Reads executed in other blocks

For PIC18FX620 and PIC18FX720 devices:
1

= Block 1 (004000-007FFFh) not protected from Table Reads executed in other blocks

= Block 1 (004000-007FFFh) protected from Table Reads executed in other blocks

bit 0

EBTR0: Table Read Protection bit
For PIC18FX520 devices:
1

= Block 0 (000800-001FFFh) not protected from Table Reads executed in other blocks

= Block 0 (000800-001FFFh) protected from Table Reads executed in other blocks

For PIC18FX620 and PIC18FX720 devices:
1

= Block 0 (000200-003FFFh) not protected from Table Reads executed in other blocks

= Block 0 (000200-003FFFh) protected from Table Reads executed in other blocks

Note 1: Unimplemented in PIC18FX520 and PIC18FX620 devices; maintain this bit set.

Legend:
R = Readable bit

P = Programmable bit

U = Unimplemented bit, read as `0'

- n = Value when device is unprogrammed

u = Unchanged from programmed state

2003 Microchip Technology Inc.

Advance Information

DS39609A-page 249

PIC18FXX20

REGISTER 23-12: CONFIG7H: CONFIGURATION REGISTER 7 HIGH (BYTE ADDRESS 30000Dh)

REGISTER 23-13: DEVICE ID REGISTER 1 FOR PIC18FXX20 DEVICES (ADDRESS 3FFFFEh)

REGISTER 23-14:

DEVICE ID REGISTER 2 FOR PIC18FXX20 DEVICES (ADDRESS 3FFFFFh)

U-0

R/P-1

U-0

EBTRB

bit 7

bit 0

bit 7

Unimplemented: Read as `0'

bit 6

EBTRB: Boot Block Table Read Protection bit
For PIC18FX520 devices:
1

= Boot Block (000000-0007FFh) not protected from Table Reads executed in other blocks

= Boot Block (000000-0007FFh) protected from Table Reads executed in other blocks

For PIC18FX620 and PIC18FX720 devices:
1

= Boot Block (000000-0001FFh) not protected from Table Reads executed in other blocks

= Boot Block (000000-0001FFh) protected from Table Reads executed in other blocks

bit 5-0

Unimplemented: Read as `0'

Legend:
R = Readable bit

P = Programmable bit

U = Unimplemented bit, read as `0'

- n = Value when device is unprogrammed

u = Unchanged from programmed state

DEV2

DEV1

DEV0

REV4

REV3

REV2

REV1

REV0

bit 7

bit 0

bit 7-5

DEV2:DEV0: Device ID bits

000

= PIC18F8720

001

= PIC18F6720

010

= PIC18F8620

011

= PIC18F6620

bit 4-0

REV4:REV0: Revision ID bits
These bits are used to indicate the device revision

Legend:
R = Readable bit

P = Programmable bit

U = Unimplemented bit, read as `0'

- n = Value when device is unprogrammed

u = Unchanged from programmed state

DEV10

DEV9

DEV8

DEV7

DEV6

DEV5

DEV4

DEV3

bit 7

bit 0

bit 7-0

DEV10:DEV3: Device ID bits
These bits are used with the DEV2:DEV0 bits in the Device ID Register 1 to identify the
part number

Legend:
R = Readable bit

P = Programmable bit

U = Unimplemented bit, read as `0'

- n = Value when device is unprogrammed

u = Unchanged from programmed state

PIC18FXX20

DS39609A-page 250

Advance Information

2003 Microchip Technology Inc.

23.2

Watchdog Timer (WDT)

The Watchdog Timer is a free running, on-chip RC
oscillator, which does not require any external compo-
nents. This RC oscillator is separate from the RC oscil-
lator of the OSC1/CLKI pin. That means that the WDT
will run, even if the clock on the OSC1/CLKI and
OSC2/CLKO/RA6 pins of the device has been stopped,
for example, by execution of a SLEEP instruction.
During normal operation, a WDT time-out generates a
device RESET (Watchdog Timer Reset). If the device is
in SLEEP mode, a WDT time-out causes the device to
wake-up and continue with normal operation (Watch-
dog Timer Wake-up). The TO bit in the RCON register
will be cleared upon a WDT time-out.
The Watchdog Timer is enabled/disabled by a device
configuration bit. If the WDT is enabled, software exe-
cution may not disable this function. When the WDTEN
configuration bit is cleared, the SWDTEN bit
enables/disables the operation of the WDT.

The WDT time-out period values may be found in the
Electrical Specifications section under parameter #31.
Values for the WDT postscaler may be assigned using
the configuration bits.

23.2.1

CONTROL REGISTER

Register 23-15 shows the WDTCON register. This is a
readable and writable register, which contains a control
bit that allows software to override the WDT enable
configuration bit, only when the configuration bit has
disabled the WDT.

REGISTER 23-15: WDTCON REGISTER

Note 1: The CLRWDT and SLEEP instructions

clear the WDT and the postscaler, if
assigned to the WDT and prevent it from
timing out and generating a device
RESET condition.

2: When a CLRWDT instruction is executed

and the postscaler is assigned to the
WDT, the postscaler count will be cleared,
but the postscaler assignment is not
changed.

U-0

R/W-0

SWDTEN

bit 7

bit 0

bit 7-1

Unimplemented: Read as `0'

bit 0

SWDTEN: Software Controlled Watchdog Timer Enable bit
1

= Watchdog Timer is on

= Watchdog Timer is turned off if the WDTEN configuration bit in the Configuration

Legend:
R = Readable bit

W = Writable bit

U = Unimplemented bit, read as `0'

- n = Value at POR

`1' = Bit is set

`0' = Bit is cleared

x = Bit is unknown

PIC18FXX20

DS39609A-page 252

Advance Information

2003 Microchip Technology Inc.

23.3

Power-down Mode (SLEEP)

Power-down mode is entered by executing a SLEEP
instruction.
If enabled, the Watchdog Timer will be cleared, but
keeps running, the PD bit (RCON<3>) is cleared, the
TO (RCON<4>) bit is set, and the oscillator driver is
turned off. The I/O ports maintain the status they had
before the SLEEP instruction was executed (driving
high, low, or hi-impedance).
For lowest current consumption in this mode, place all
I/O pins at either V

or V

, ensure no external cir-

cuitry is drawing current from the I/O pin, power-down
the A/D and disable external clocks. Pull all I/O pins
that are hi-impedance inputs, high or low externally, to
avoid switching currents caused by floating inputs. The
T0CKI input should also be at V

or V

for lowest

current consumption. The contribution from on-chip
pull-ups on PORTB should be considered.
The MCLR pin must be at a logic high level (V

IHMC

23.3.1

WAKE-UP FROM SLEEP

The device can wake-up from SLEEP through one of
the following events:
1.

External RESET input on MCLR pin.

Watchdog Timer Wake-up (if WDT was
enabled).

Interrupt from INT pin, RB port change or a
peripheral interrupt.

The following peripheral interrupts can wake the device
from SLEEP:
1.

PSP read or write.

TMR1 interrupt. Timer1 must be operating as an
asynchronous counter.

TMR3 interrupt. Timer3 must be operating as an
asynchronous counter.

CCP Capture mode interrupt.

Special event trigger (Timer1 in Asynchronous
mode using an external clock).

MSSP (START/STOP) bit detect interrupt.

MSSP transmit or receive in Slave mode
(SPI/I

C).

USART RX or TX (Synchronous Slave mode).

A/D conversion (when A/D clock source is RC).

10. EEPROM write operation complete.
11. LVD interrupt.
Other peripherals cannot generate interrupts, since
during SLEEP, no on-chip clocks are present.

External MCLR Reset will cause a device RESET. All
other events are considered a continuation of program
execution and will cause a "wake-up". The TO and PD
bits in the RCON register can be used to determine the
cause of the device RESET. The PD bit, which is set on
power-up, is cleared when SLEEP is invoked. The TO
bit is cleared if a WDT time-out occurred (and caused
wake-up).
When the SLEEP instruction is being executed, the next
instruction (PC + 2) is pre-fetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be set (enabled). Wake-up is
regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
instruction after the SLEEP instruction. If the GIE bit is
set (enabled), the device executes the instruction after
the SLEEP instruction and then branches to the inter-
rupt address. In cases where the execution of the
instruction following SLEEP is not desirable, the user
should have a NOP after the SLEEP instruction.

23.3.2

WAKE-UP USING INTERRUPTS

When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
� If an interrupt condition (interrupt flag bit and inter-

rupt enable bits are set) occurs before the execu-
tion of a SLEEP instruction, the SLEEP instruction
will complete as a NOP. Therefore, the WDT and
WDT postscaler will not be cleared, the TO bit will
not be set and PD bits will not be cleared.

� If the interrupt condition occurs during or after

the execution of a SLEEP instruction, the device
will immediately wake-up from SLEEP. The
SLEEP

instruction will be completely executed

before the wake-up. Therefore, the WDT and
WDT postscaler will be cleared, the TO bit will be
set and the PD bit will be cleared.

Even if the flag bits were checked before executing a
SLEEP

instruction, it may be possible for flag bits to

become set before the SLEEP instruction completes. To
determine whether a SLEEP instruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
To ensure that the WDT is cleared, a CLRWDT instruction
should be executed before a SLEEP instruction.

2003 Microchip Technology Inc.

Advance Information

DS39609A-page 253

PIC18FXX20

FIGURE 23-2:

WAKE-UP FROM SLEEP THROUGH INTERRUPT

(1,2)

23.4

Program Verification and
Code Protection

The overall structure of the code protection on the
PIC18 FLASH devices differs significantly from other
PICmicro devices. The user program memory is
divided on binary boundaries into individual blocks,
each of which has three separate code protection bits
associated with it:
� Code Protect bit (CPn)
� Write Protect bit (WRTn)
� External Block Table Read bit (EBTRn)
The code protection bits are located in Configuration
Registers 5L through 7H. Their locations within the
registers are summarized in Table 23-3.

In the PIC18FXX20 family, the block size varies with
the size of the user program memory. For PIC18FX520
devices, program memory is divided into four blocks of
8 Kbytes each. The first block is further divided into a
boot block of 2 Kbytes and a second block (Block 0) of
6 Kbytes, for a total of five blocks. The organization of
the blocks and their associated code protection bits are
shown in Figure 23-3.
For PIC18FX620 and PIC18FX720 devices, program
memory is divided into blocks of 16 Kbytes. The first
block is further divided into a boot block of 512 bytes
and a second block (Block 0) of 15.5 Kbytes, for a total
of nine blocks. This produces five blocks for 64-Kbyte
devices, and nine for 128-Kbyte devices. The organiza-
tion of the blocks and their associated code protection
bits are shown in Figure 23-4.

TABLE 23-3:

SUMMARY OF CODE PROTECTION REGISTERS

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

CLKO

(4)

INT pin

INTF flag

(INTCON<1>)

GIEH bit

(INTCON<7>)

INSTRUCTION FLOW

Instruction

Fetched

Instruction

Executed

PC+2

PC+4

Inst(PC) = SLEEP

Inst(PC - 1)

Inst(PC + 2)

SLEEP

Processor in

SLEEP

Interrupt Latency

(3)

Inst(PC + 4)

Inst(PC + 2)

Inst(0008h)

Inst(000Ah)

Inst(0008h)

Dummy Cycle

PC + 4

0008h

000Ah

Dummy Cycle

OST(2)

PC+4

Note

XT, HS or LP Oscillator mode assumed.

GIE = 1 assumed. In this case, after wake-up, the processor jumps to the interrupt routine. If GIE = 0, execution will continue in-line.

OST

= 1024 T

OSC

(drawing not to scale). This delay will not occur for RC and EC Osc modes.

CLKO is not available in these Osc modes, but shown here for timing reference.

File Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

300008h

CONFIG5L

CP7*

CP6*

CP5*

CP4*

CP3

CP2

CP1

CP0

300009h

CONFIG5H

CPD

CPB

30000Ah

CONFIG6L

WRT7*

WRT6*

WRT5*

WRT4*

WRT3

WRT2

WRT1

WRT0

30000Bh

CONFIG6H

WRTD

WRTB

WRTC

30000Ch

CONFIG7L

EBTR7*

EBTR6*

EBTR5*

EBTR4*

EBTR3

EBTR2

EBTR1

EBTR0

30000Dh

CONFIG7H

EBTRB

Legend: Shaded cells are unimplemented.

* Unimplemented in PIC18FX520 and PIC18FX620 devices.

2003 Microchip Technology Inc.

Advance Information

DS39609A-page 255

PIC18FXX20

23.4.1

PROGRAM MEMORY
CODE PROTECTION

The user memory may be read to, or written from, any
location using the Table Read and Table Write instruc-
tions. The device ID may be read with Table Reads.
The configuration registers may be read and written
with the Table Read and Table Write instructions.
In User mode, the CPn bits have no direct effect. CPn
bits inhibit external reads and writes. A block of user
memory may be protected from Table Writes if the
WRTn configuration bit is `0'. The EBTRn bits control
Table Reads. For a block of user memory with the
EBTRn bit set to `0', a Table Read instruction that exe-
cutes from within that block is allowed to read. A Table
Read instruction that executes from a location outside
of that block is not allowed to read, and will result in

reading `0's. Figures 23-5 through 23-7 illustrate Table
Write and Table Read protection, using devices with a
16-Kbyte block size as the models. The principles illus-
trated are identical for devices with an 8-Kbyte block
size.

FIGURE 23-5:

TABLE WRITE (WRTn) DISALLOWED

Note:

Code protection bits may only be written to
a `0' from a `1' state. It is not possible to
write a `1' to a bit in the `0' state. Code pro-
tection bits are only set to `1' by a full chip
erase or block erase function. The full chip
erase and block erase functions can only
be initiated via ICSP or an external
programmer.

000000h

0001FFh

000200h

003FFFh

004000h

007FFFh

008000h

00BFFFh

00C000h

00FFFFh

WRTB,EBTRB = 11

WRT0,EBTR0 = 01

WRT1,EBTR1 = 11

WRT2,EBTR2 = 11

WRT3,EBTR3 = 11

TBLWT *

TBLPTR = 000FFFh

PC = 003FFEh

TBLWT *

PC = 008FFEh

Register Values

Program Memory

Configuration Bit Settings

Results: All Table Writes disabled to Block n whenever WRTn = 0

2003 Microchip Technology Inc.

Advance Information

DS39609A-page 257

PIC18FXX20

23.4.2

DATA EEPROM
CODE PROTECTION

The entire Data EEPROM is protected from external
reads and writes by two bits: CPD and WRTD. CPD
inhibits external reads and writes of Data EEPROM.
WRTD inhibits external writes to Data EEPROM. The
CPU can continue to read and write Data EEPROM,
regardless of the protection bit settings.

23.4.3

CONFIGURATION REGISTER
PROTECTION

The configuration registers can be write protected. The
WRTC bit controls protection of the Configuration reg-
isters. In User mode, the WRTC bit is readable only.
WRTC can only be written via ICSP or an external
programmer.

23.5

ID Locations

Eight memory locations (200000h - 200007h) are des-
ignated as ID locations, where the user can store
checksum or other code identification numbers. These
locations are accessible during normal execution
through the TBLRD and TBLWT instructions, or during
program/verify. The ID locations can be read when the
device is code protected.

23.6

In-Circuit Serial Programming

PIC18FXX20 microcontrollers can be serially pro-
grammed while in the end application circuit. This is
simply done with two lines for clock and data, and three
other lines for power, ground and the programming
voltage. This allows customers to manufacture boards
with unprogrammed devices, and then program the
microcontroller just before shipping the product. This
also allows the most recent firmware, or a custom
firmware to be programmed.

23.7

In-Circuit Debugger

When the DEBUG bit in Configuration register
CONFIG4L is programmed to a '0', the In-Circuit
Debugger functionality is enabled. This function allows
simple debugging functions when used with MPLAB

�

IDE. When the microcontroller has this feature
enabled, some of the resources are not available for
general use. Table 23-4 shows which features are
consumed by the background debugger.

TABLE 23-4:

DEBUGGER RESOURCES

To use the In-Circuit Debugger function of the micro-
controller, the design must implement In-Circuit Serial
Programming connections to MCLR/V

, V

, GND,

RB7 and RB6. This will interface to the In-Circuit
Debugger module available from Microchip, or one of
the third party development tool companies.

23.8

Low Voltage ICSP Programming

The LVP bit Configuration register, CONFIG4L,
enables low voltage ICSP programming. This mode
allows the microcontroller to be programmed via ICSP
using a V

source in the operating voltage range. This

only means that V

does not have to be brought to

IHH

, but can instead be left at the normal operating

voltage. In this mode, the RB5/PGM pin is dedicated to
the programming function and ceases to be a general
purpose I/O pin. During programming, V

is applied to

the MCLR/V

pin. To enter Programming mode, V

must be applied to the RB5/PGM, provided the LVP bit
is set. The LVP bit defaults to a (`1') from the factory.

If Low Voltage Programming mode is not used, the LVP
bit can be programmed to a '0' and RB5/PGM becomes
a digital I/O pin. However, the LVP bit may only be pro-
grammed when programming is entered with V

IHH

MCLR/V

It should be noted that once the LVP bit is programmed
to `0', only the High Voltage Programming mode is
available and only High Voltage Programming mode
can be used to program the device.
When using low voltage ICSP, the part must be sup-
plied 4.5V to 5.5V, if a bulk erase will be executed. This
includes reprogramming of the code protect bits from
an on state to an off state. For all other cases of low
voltage ICSP, the part may be programmed at the nor-
mal operating voltage. This means unique user IDs, or
user code can be reprogrammed or added.

Note:

When performing in-circuit serial program-
ming, verify that power is connected to all
V

and AV

pins of the microcontroller,

and that all V

and AV

pins are

grounded.

I/O pins

RB6, RB7

Stack

2 levels

Program Memory

Last 576 bytes

Data Memory

Last 10 bytes

Note 1: The High Voltage Programming mode is

always available, regardless of the state
of the LVP bit, by applying V

IHH

to the

MCLR pin.

2: While in Low Voltage ICSP mode, the

RB5 pin can no longer be used as a gen-
eral purpose I/O pin, and should be held
low during normal operation.

3: When using low voltage ICSP program-

ming (LVP) and the pull-ups on PORTB
are enabled, bit 5 in the TRISB register
must be cleared to disable the pull-up on
RB5 and ensure the proper operation of
the device.

2003 Microchip Technology Inc.

Advance Information

DS39609A-page 259

PIC18FXX20

24.0 INSTRUCTION SET SUMMARY

The PIC18 instruction set adds many enhancements to
the previous PICmicro instruction sets, while maintain-
ing an easy migration from these PICmicro instruction
sets.
Most instructions are a single program memory word
(16 bits), but there are three instructions that require
two program memory locations.
Each single word instruction is a 16-bit word divided
into an OPCODE, which specifies the instruction type
and one or more operands, which further specify the
operation of the instruction.
The instruction set is highly orthogonal and is grouped
into four basic categories:
� Byte-oriented operations
� Bit-oriented operations
� Literal operations
� Control operations
The PIC18 instruction set summary in Table 24-2 lists
byte-oriented, bit-oriented, literal and control
operations. Table 24-1 shows the opcode field
descriptions.
Most byte-oriented instructions have three operands:
1.

The file register (specified by `f')

The destination of the result
(specified by `d')

The accessed memory
(specified by `a')

The file register designator 'f' specifies which file
register is to be used by the instruction.
The destination designator `d' specifies where the
result of the operation is to be placed. If 'd' is zero, the
result is placed in the WREG register. If 'd' is one, the
result is placed in the file register specified in the
instruction.
All bit-oriented instructions have three operands:
1.

The file register (specified by `f')

The bit in the file register
(specified by `b')

The accessed memory
(specified by `a')

The bit field designator 'b' selects the number of the bit
affected by the operation, while the file register desig-
nator 'f' represents the number of the file in which the
bit is located.

The literal instructions may use some of the following
operands:
� A literal value to be loaded into a file register

(specified by `k')

� The desired FSR register to load the literal value

into (specified by `f')

� No operand required

(specified by `--')

The control instructions may use some of the following
operands:
� A program memory address (specified by `n')
� The mode of the Call or Return instructions

(specified by `s')

� The mode of the Table Read and Table Write

instructions (specified by `m')

� No operand required

(specified by `--')

All instructions are a single word, except for three dou-
ble-word instructions. These three instructions were
made double-word instructions so that all the required
information is available in these 32 bits. In the second
word, the 4 MSbs are `1's. If this second word is exe-
cuted as an instruction (by itself), it will execute as a
NOP

All single word instructions are executed in a single
instruction cycle, unless a conditional test is true, or the
program counter is changed as a result of the instruc-
tion. In these cases, the execution takes two instruction
cycles, with the additional instruction cycle(s) executed
as a NOP.
The double-word instructions execute in two instruction
cycles.
One instruction cycle consists of four oscillator periods.
Thus, for an oscillator frequency of 4 MHz, the normal
instruction execution time is 1

祍. If a conditional test is

true, or the program counter is changed as a result of
an instruction, the instruction execution time is 2

祍.

Two-word branch instructions (if true) would take 3

祍.

Figure 24-1 shows the general formats that the
instructions can have.
All examples use the format `nnh' to represent a hexa-
decimal number, where `h' signifies a hexadecimal
digit.
The Instruction Set Summary, shown in Table 24-2,
lists the instructions recognized by the Microchip
Assembler (MPASM

Section 24.1 provides a description of each instruction.

PIC18FXX20

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TABLE 24-1:

OPCODE FIELD DESCRIPTIONS

Field

Description

RAM access bit
a = 0: RAM location in Access RAM (BSR register is ignored)
a = 1: RAM bank is specified by BSR register

bbb

Bit address within an 8-bit file register (0 to 7)

BSR

Bank Select Register. Used to select the current RAM bank.

Destination select bit
d = 0: store result in WREG
d = 1: store result in file register f.

dest

Destination either the WREG register or the specified register file location

8-bit Register file address (0x00 to 0xFF)

12-bit Register file address (0x000 to 0xFFF). This is the source address.

12-bit Register file address (0x000 to 0xFFF). This is the destination address.

Literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value)

label

Label name

The mode of the TBLPTR register for the Table Read and Table Write instructions.
Only used with Table Read and Table Write instructions:

No Change to register (such as TBLPTR with Table Reads and Writes)

Post-Increment register (such as TBLPTR with Table Reads and Writes)

Post-Decrement register (such as TBLPTR with Table Reads and Writes)

Pre-Increment register (such as TBLPTR with Table Reads and Writes)

The relative address (2's complement number) for relative branch instructions, or the direct address for
Call/Branch and Return instructions

PRODH

Product of Multiply high byte

PRODL

Product of Multiply low byte

Fast Call/Return mode select bit
s = 0: do not update into/from shadow registers
s = 1: certain registers loaded into/from shadow registers (Fast mode)

Unused or Unchanged

WREG

Working register (accumulator)

Don't care (0 or 1)
The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all
Microchip software tools.

TBLPTR

21-bit Table Pointer (points to a Program Memory location)

TABLAT

8-bit Table Latch

TOS

Top-of-Stack

Program Counter

PCL

Program Counter Low Byte

PCH

Program Counter High Byte

PCLATH

Program Counter High Byte Latch

PCLATU

Program Counter Upper Byte Latch

GIE

Global Interrupt Enable bit

WDT

Watchdog Timer

Time-out bit

Power-down bit

C, DC, Z, OV, N

ALU status bits Carry, Digit Carry, Zero, Overflow, Negative

[ ]

Optional

( )

Contents

Assigned to

< >

In the set of

italics

User defined term (font is courier)

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TABLE 24-2:

PIC18FXXX INSTRUCTION SET

Mnemonic,

Operands

Description

Cycles

16-Bit Instruction Word

Status

Affected

Notes

MSb

LSb

BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ADDWFC
ANDWF
CLRF
COMF
CPFSEQ
CPFSGT
CPFSLT
DECF
DECFSZ
DCFSNZ
INCF
INCFSZ
INFSNZ
IORWF
MOVF
MOVFF

MOVWF
MULWF
NEGF
RLCF
RLNCF
RRCF
RRNCF
SETF
SUBFWB

SUBWF
SUBWFB

SWAPF
TSTFSZ
XORWF

f, d, a
f, d, a
f, d, a
f, a
f, d, a
f, a
f, a
f, a
f, d, a
f, d, a
f, d, a
f, d, a
f, d, a
f, d, a
f, d, a
f, d, a
f

, f

f, a
f, a
f, a
f, d, a
f, d, a
f, d, a
f, d, a
f, a
f, d, a

f, d, a
f, d, a

f, d, a
f, a
f, d, a

Add WREG and f
Add WREG and Carry bit to f
AND WREG with f
Clear f
Complement f
Compare f with WREG, skip =
Compare f with WREG, skip >
Compare f with WREG, skip <
Decrement f
Decrement f, Skip if 0
Decrement f, Skip if Not 0
Increment f
Increment f, Skip if 0
Increment f, Skip if Not 0
Inclusive OR WREG with f
Move f
Move f

(source) to 1st word

(destination)2nd word

Move WREG to f
Multiply WREG with f
Negate f
Rotate Left f through Carry
Rotate Left f (No Carry)
Rotate Right f through Carry
Rotate Right f (No Carry)
Set f
Subtract f from WREG with
borrow
Subtract WREG from f
Subtract WREG from f with
borrow
Swap nibbles in f
Test f, skip if 0
Exclusive OR WREG with f

1
1
1
1
1
1 (2 or 3)
1 (2 or 3)
1 (2 or 3)
1
1 (2 or 3)
1 (2 or 3)
1
1 (2 or 3)
1 (2 or 3)
1
1
2

1
1
1
1
1
1
1
1
1

1
1

1
1 (2 or 3)
1

0010

0001

0110

0001

0110

0000

0010

0100

0010

0011

0100

0001

0101

1100

1111

0110

0000

0110

0011

0100

0011

0100

0110

0101

0011

0110

0001

01da0

0da

01da

101a

11da

001a

010a

000a

01da

11da

10da

11da

10da

00da

ffff

111a

001a

110a

01da

00da

100a

01da

11da

10da

011a

10da

ffff

C, DC, Z, OV, N
C, DC, Z, OV, N
Z, N
Z
Z, N
None
None
None
C, DC, Z, OV, N
None
None
C, DC, Z, OV, N
None
None
Z, N
Z, N
None

None
None
C, DC, Z, OV, N
C, Z, N
Z, N
C, Z, N
Z, N
None
C, DC, Z, OV, N

C, DC, Z, OV, N
C, DC, Z, OV, N

None
None
Z, N

1, 2
1, 2
1,2
2
1, 2
4
4
1, 2
1, 2, 3, 4
1, 2, 3, 4
1, 2
1, 2, 3, 4
4
1, 2
1, 2
1

1, 2

4
1, 2

BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
BTG

f, b, a
f, b, a
f, b, a
f, b, a
f, d, a

Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
Bit Toggle f

1
1
1 (2 or 3)
1 (2 or 3)
1

1001

1000

1011

1010

0111

bbba

ffff

None
None
None
None
None

1, 2
1, 2
3, 4
3, 4
1, 2

Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value

present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an
external device, the data will be written back with a '0'.

2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if

assigned.

3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is

executed as a NOP.

4: Some instructions are 2-word instructions. The second word of these instructions will be executed as a NOP, unless the

first word of the instruction retrieves the information embedded in these 16-bits. This ensures that all program memory
locations have a valid instruction.

5: If the Table Write starts the write cycle to internal memory, the write will continue until terminated.

2003 Microchip Technology Inc.

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PIC18FXX20

CONTROL OPERATIONS
BC
BN
BNC
BNN
BNOV
BNZ
BOV
BRA
BZ
CALL

CLRWDT
DAW
GOTO

NOP
NOP
POP
PUSH
RCALL
RESET
RETFIE

RETLW
RETURN
SLEEP

n
n
n
n
n
n
n
n
n
n, s

--
--
n

--
--
--
--
n

k
s
--

Branch if Carry
Branch if Negative
Branch if Not Carry
Branch if Not Negative
Branch if Not Overflow
Branch if Not Zero
Branch if Overflow
Branch Unconditionally
Branch if Zero
Call subroutine1st word

2nd word

Clear Watchdog Timer
Decimal Adjust WREG
Go to address 1st word

2nd word

No Operation
No Operation
Pop top of return stack (TOS)
Push top of return stack (TOS)
Relative Call
Software device RESET
Return from interrupt enable

Return with literal in WREG
Return from Subroutine
Go into Standby mode

1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
2
1 (2)
1 (2)
1 (2)
2

1
1
2

1
1
1
1
2
1
2

2
2
1

1110

1101

1110

1111

0000

1110

1111

0000

1111

0000

1101

0000

0010

0110

0011

0111

0101

0001

0100

0nnn

0000

110s

kkkk

0000

1111

kkkk

0000

xxxx

0000

1nnn

0000

1100

0000

nnnn

kkkk

0000

kkkk

0000

xxxx

0000

nnnn

1111

0001

kkkk

0001

0000

nnnn

kkkk

0100

0111

kkkk

0000

xxxx

0110

0101

nnnn

1111

000s

kkkk

001s

0011

None
None
None
None
None
None
None
None
None
None

TO, PD
C
None

None
None
None
None
None
All
GIE/GIEH,
PEIE/GIEL
None
None
TO, PD

TABLE 24-2:

PIC18FXXX INSTRUCTION SET (CONTINUED)

Mnemonic,

Operands

Description

Cycles

16-Bit Instruction Word

Status

Affected

Notes

MSb

LSb

Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value

present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an
external device, the data will be written back with a '0'.

2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if

assigned.

3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is

executed as a NOP.

4: Some instructions are 2-word instructions. The second word of these instructions will be executed as a NOP, unless the

first word of the instruction retrieves the information embedded in these 16-bits. This ensures that all program memory
locations have a valid instruction.

5: If the Table Write starts the write cycle to internal memory, the write will continue until terminated.

PIC18FXX20

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LITERAL OPERATIONS
ADDLW
ANDLW
IORLW
LFSR

MOVLB
MOVLW
MULLW
RETLW
SUBLW
XORLW

k
k
k
f, k

k
k
k
k
k
k

Add literal and WREG
AND literal with WREG
Inclusive OR literal with WREG
Move literal (12-bit) 2nd word

to FSRx 1st word

Move literal to BSR<3:0>
Move literal to WREG
Multiply literal with WREG
Return with literal in WREG
Subtract WREG from literal
Exclusive OR literal with WREG

1
1
1
2

1
1
1
2
1
1

0000

1110

1111

0000

1111

1011

1001

1110

0000

0001

1110

1101

1100

1000

1010

kkkk

00ff

kkkk

0000

kkkk

C, DC, Z, OV, N
Z, N
Z, N
None

None
None
None
None
C, DC, Z, OV, N
Z, N

DATA MEMORY

PROGRAM MEMORY OPERATIONS

TBLRD*
TBLRD*+
TBLRD*-
TBLRD+*
TBLWT*
TBLWT*+
TBLWT*-
TBLWT+*

Table Read
Table Read with post-increment
Table Read with post-decrement
Table Read with pre-increment
Table Write
Table Write with post-increment
Table Write with post-decrement
Table Write with pre-increment

2 (5)

0000

1000

1001

1010

1011

1100

1101

1110

1111

None
None
None
None
None
None
None
None

TABLE 24-2:

PIC18FXXX INSTRUCTION SET (CONTINUED)

Mnemonic,

Operands

Description

Cycles

16-Bit Instruction Word

Status

Affected

Notes

MSb

LSb

Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value

present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an
external device, the data will be written back with a '0'.

2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if

assigned.

3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is

executed as a NOP.

4: Some instructions are 2-word instructions. The second word of these instructions will be executed as a NOP, unless the

first word of the instruction retrieves the information embedded in these 16-bits. This ensures that all program memory
locations have a valid instruction.

5: If the Table Write starts the write cycle to internal memory, the write will continue until terminated.

2003 Microchip Technology Inc.

Advance Information

DS39609A-page 269

PIC18FXX20

BNC

Branch if Not Carry

Syntax:

[ label ] BNC n

Operands:

-128

n 127

Operation:

if carry bit is '0'
(PC) + 2 + 2n

Status Affected:

None

Encoding:

1110

0011

nnnn

Description:

If the Carry bit is `0', then the
program will branch.
The 2's complement number `2n' is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then
a two-cycle instruction.

Words:

Cycles:

1(2)

Q Cycle Activity:
If Jump:

Decode

Read literal

'n'

Process

Data

Write to PC

operation

If No Jump:

Decode

Read literal

'n'

Process

Data

operation

Example:

HERE

BNC

Jump

Before Instruction

address (HERE)

After Instruction

If Carry

= address

(Jump)

If Carry

= address (HERE+2)

BNN

Branch if Not Negative

Syntax:

[ label ] BNN n

Operands:

-128

n 127

Operation:

if negative bit is '0'
(PC) + 2 + 2n

Status Affected:

None

Encoding:

1110

0111

nnnn

Description:

If the Negative bit is `0', then the
program will branch.
The 2's complement number `2n' is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then
a two-cycle instruction.

Words:

Cycles:

1(2)

Q Cycle Activity:
If Jump:

Decode

Read literal

'n'

Process

Data

Write to PC

operation

If No Jump:

Decode

Read literal

'n'

Process

Data

operation

Example:

HERE

BNN

Jump

Before Instruction

address (HERE)

After Instruction

If Negative

= address (Jump)

If Negative

= address (HERE+2)

PIC18FXX20

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BNOV

Branch if Not Overflow

Syntax:

[ label ] BNOV n

Operands:

-128

n 127

Operation:

if overflow bit is '0'
(PC) + 2 + 2n

Status Affected:

None

Encoding:

1110

0101

nnnn

Description:

If the Overflow bit is `0', then the
program will branch.
The 2's complement number `2n' is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then
a two-cycle instruction.

Words:

Cycles:

1(2)

Q Cycle Activity:
If Jump:

Decode

Read literal

'n'

Process

Data

Write to PC

operation

If No Jump:

Decode

Read literal

'n'

Process

Data

operation

Example:

HERE

BNOV

Jump

Before Instruction

address (HERE)

After Instruction

If Overflow

= address (Jump)

If Overflow

= address (HERE+2)

BNZ

Branch if Not Zero

Syntax:

[ label ] BNZ n

Operands:

-128

n 127

Operation:

if zero bit is '0'
(PC) + 2 + 2n

Status Affected:

None

Encoding:

1110

0001

nnnn

Description:

If the Zero bit is `0', then the
program will branch.
The 2's complement number `2n' is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then
a two-cycle instruction.

Words:

Cycles:

1(2)

Q Cycle Activity:
If Jump:

Decode

Read literal

'n'

Process

Data

Write to PC

operation

If No Jump:

Decode

Read literal

'n'

Process

Data

operation

Example:

HERE

BNZ

Jump

Before Instruction

address (HERE)

After Instruction

If Zero

= address

(Jump)

If Zero

= address

(HERE+2)

PIC18FXX20

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BTFSC

Bit Test File, Skip if Clear

Syntax:

[ label ] BTFSC f,b[,a]

Operands:

f 255

b 7

[0,1]

Operation:

skip if (f<b>) = 0

Status Affected:

None

Encoding:

1011

bbba

ffff

Description:

If bit 'b' in register `f' is 0, then the
next instruction is skipped.
If bit 'b' is 0, then the next instruction
fetched during the current instruction
execution is discarded, and a NOP is
executed instead, making this a
two-cycle instruction. If `a' is 0, the
Access Bank will be selected, over-
riding the BSR value. If `a' = 1, then
the bank will be selected as per the
BSR value (default).

Words:

Cycles:

1(2)
Note: 3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Decode

Read

Process Data

operation

If skip:

operation

If skip and followed by 2-word instruction:

operation

Example:

HERE

FALSE

TRUE

BTFSC

FLAG, 1, 0

Before Instruction

address (HERE)

After Instruction

If FLAG<1>

= address (TRUE)

If FLAG<1>

= address (FALSE)

BTFSS

Bit Test File, Skip if Set

Syntax:

[ label ] BTFSS f,b[,a]

Operands:

f 255

b < 7

[0,1]

Operation:

skip if (f<b>) = 1

Status Affected:

None

Encoding:

1010

bbba

ffff

Description:

If bit 'b' in register 'f' is 1, then the
next instruction is skipped.
If bit 'b' is 1, then the next instruction
fetched during the current instruc-
tion execution, is discarded and a
NOP

is executed instead, making this

a two-cycle instruction. If `a' is 0, the
Access Bank will be selected, over-
riding the BSR value. If `a' = 1, then
the bank will be selected as per the
BSR value (default).

Words:

Cycles:

1(2)
Note:

3 cycles if skip and followed
by a 2-word instruction.

Q Cycle Activity:

Decode

Read

Process Data

operation

If skip:

operation

If skip and followed by 2-word instruction:

operation

Example:

HERE

FALSE

TRUE

BTFSS

FLAG, 1, 0

Before Instruction

= address (HERE)

After Instruction

If FLAG<1>

= address (FALSE)

If FLAG<1>

= address

(TRUE)

PIC18FXX20

DS39609A-page 274

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Branch if Zero

Syntax:

[ label ] BZ n

Operands:

-128

n 127

Operation:

if Zero bit is '1'
(PC) + 2 + 2n

Status Affected:

None

Encoding:

1110

0000

nnnn

Description:

If the Zero bit is `1', then the
program will branch.
The 2's complement number `2n' is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then
a two-cycle instruction.

Words:

Cycles:

1(2)

Q Cycle Activity:
If Jump:

Decode

Read literal

'n'

Process

Data

Write to PC

operation

If No Jump:

Decode

Read literal

'n'

Process

Data

operation

Example:

HERE

Jump

Before Instruction

address (HERE)

After Instruction

If Zero

= address (Jump)

If Zero

= address (HERE+2)

CALL

Subroutine Call

Syntax:

[ label ] CALL k [,s]

Operands:

k 1048575

[0,1]

Operation:

(PC) + 4

TOS,

PC<20:1>,

if s = 1
(W)

WS,

(STATUS)

STATUSS,

(BSR)

BSRS

Status Affected:

None

Encoding:
1st word (k<7:0>)
2nd word(k<19:8>)

1110

1111

110s

kkk

kkkk

Description:

Subroutine call of entire 2-Mbyte
memory range. First, return
address (PC+ 4) is pushed onto the
return stack. If `s' = 1, the W,
STATUS and BSR registers are
also pushed into their respective
shadow registers, WS, STATUSS
and BSRS. If 's' = 0, no update
occurs (default). Then, the 20-bit
value `k' is loaded into PC<20:1>.
CALL

is a two-cycle instruction.

Words:

Cycles:

Q Cycle Activity:

Decode

Read literal

'k'<7:0>,

Push PC to

stack

Read literal

'k'<19:8>,

Write to PC

operation

Example:

HERE

CALL THERE,1

Before Instruction

address (HERE)

After Instruction

address (THERE)

TOS

address (HERE + 4)

BSRS

BSR

STATUSS= STATUS

PIC18FXX20

DS39609A-page 276

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COMF

Complement f

Syntax:

[ label ] COMF f [,d [,a]

Operands:

f 255

[0,1]

Operation:

dest

Status Affected:

N, Z

Encoding:

0001

11da

ffff

Description:

The contents of register 'f' are com-
plemented. If 'd' is 0, the result is
stored in W. If 'd' is 1, the result is
stored back in register 'f' (default). If
`a' is 0, the Access Bank will be
selected, overriding the BSR value.
If `a' = 1, then the bank will be
selected as per the BSR value
(default).

Words:

Cycles:

Q Cycle Activity:

Decode

Read

Process

Data

Write to

destination

Example:

COMF

REG,

0, 0

Before Instruction

REG

0x13

After Instruction

REG

0x13

0xEC

( f)

CPFSEQ

Compare f with W, skip if f = W

Syntax:

[ label ] CPFSEQ f [,a]

Operands:

f 255

[0,1]

Operation:

(f) � (W),
skip if (f) = (W)
(unsigned comparison)

Status Affected:

None

Encoding:

0110

001a

ffff

Description:

Compares the contents of data
memory location 'f' to the contents
of W by performing an unsigned
subtraction.
If 'f' = W

then the fetched instruc-

tion is discarded and a NOP is exe-
cuted instead, making this a
two-cycle instruction. If `a' is 0, the
Access Bank will be selected, over-
riding the BSR value. If `a' = 1, then
the bank will be selected as per the
BSR value (default).

Words:

Cycles:

1(2)
Note: 3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Decode

Read

Process

Data

operation

If skip:

operation

If skip and followed by 2-word instruction:

operation

Example:

HERE CPFSEQ REG, 0

NEQUAL :

EQUAL :

Before Instruction

PC Address

HERE

REG

After Instruction

If REG

PC =

Address (EQUAL)

If REG

PC =

Address (NEQUAL)

2003 Microchip Technology Inc.

Advance Information

DS39609A-page 277

PIC18FXX20

CPFSGT

Compare f with W, skip if f > W

Syntax:

[ label ] CPFSGT f [,a]

Operands:

f 255

[0,1]

Operation:

(f)

- (W),

skip if (f) > (W)
(unsigned comparison)

Status Affected:

None

Encoding:

0110

010a

ffff

Description:

Compares the contents of data
memory location 'f' to the contents
of the W by performing an
unsigned subtraction.
If the contents of 'f' are greater than
the contents of WREG

then the

fetched instruction is discarded and
a NOP is executed instead, making
this a two-cycle instruction. If `a' is
0, the Access Bank will be
selected, overriding the BSR value.
If `a' = 1, then the bank will be
selected as per the BSR value
(default).

Words:

Cycles:

1(2)
Note: 3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Decode

Read

Process

Data

operation

If skip:

operation

If skip and followed by 2-word instruction:

operation

Example:

HERE CPFSGT REG, 0

NGREATER :

GREATER :

Before Instruction

PC =

Address (HERE)

After Instruction

If REG

> W;

PC =

Address (GREATER)

If REG

= Address (NGREATER)

CPFSLT

Compare f with W, skip if f < W

Syntax:

[ label ] CPFSLT f [,a]

Operands:

f 255

[0,1]

Operation:

(f) �

(W),

skip if (f) < (W)
(unsigned comparison)

Status Affected:

None

Encoding:

0110

000a

ffff

Description:

Compares the contents of data
memory location 'f' to the contents
of W by performing an unsigned
subtraction.
If the contents of 'f' are less than
the contents of W, then the fetched
instruction is discarded and a NOP
is executed instead, making this a
two-cycle instruction. If `a' is 0, the
Access Bank will be selected. If `a'
is 1, the BSR will not be overridden
(default).

Words:

Cycles:

1(2)
Note: 3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Decode

Read

Process

Data

operation

If skip:

operation

If skip and followed by 2-word instruction:

operation

Example:

HERE CPFSLT REG, 1

NLESS :

LESS :

Before Instruction

PC =

Address (HERE)

After Instruction

If REG

= Address (LESS)

If REG

PC =

Address (NLESS)

2003 Microchip Technology Inc.

Advance Information

DS39609A-page 279

PIC18FXX20

DECFSZ

Decrement f, skip if 0

Syntax:

[ label ] DECFSZ f [,d [,a]]

Operands:

f 255

[0,1]

Operation:

(f) � 1

dest,

skip if result = 0

Status Affected:

None

Encoding:

0010

11da

ffff

Description:

The contents of register 'f' are dec-
remented. If 'd' is 0, the result is
placed in W. If 'd' is 1, the result is
placed back in register 'f' (default).
If the result is 0, the next instruc-
tion, which is already fetched, is
discarded and a NOP is executed
instead, making it a two-cycle
instruction. If `a' is 0, the Access
Bank will be selected, overriding
the BSR value. If `a' = 1, then the
bank will be selected as per the
BSR value (default).

Words:

Cycles:

1(2)
Note: 3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Decode

Read

Process

Data

Write to

destination

If skip:

operation

If skip and followed by 2-word instruction:

operation

Example:

HERE DECFSZ CNT, 1, 1

GOTO LOOP

CONTINUE

Before Instruction

PC =

Address (HERE)

After Instruction

CNT

CNT - 1

If CNT

PC = Address (CONTINUE)

If CNT

PC = Address (HERE+2)

DCFSNZ

Decrement f, skip if not 0

Syntax:

[label] DCFSNZ f [,d [,a]

Operands:

f 255

[0,1]

Operation:

(f) � 1

dest,

skip if result

Status Affected:

None

Encoding:

0100

11da

ffff

Description:

The contents of register 'f' are dec-
remented. If 'd' is 0, the result is
placed in W. If 'd' is 1, the result is
placed back in register 'f' (default).
If the result is not 0, the next
instruction, which is already
fetched, is discarded, and a NOP is
executed instead, making it a
two-cycle instruction. If `a' is 0, the
Access Bank will be selected,
overriding the BSR value. If `a' = 1,
then the bank will be selected as
per the BSR value (default).

Words:

Cycles:

1(2)
Note: 3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Decode

Read

Process

Data

Write to

destination

If skip:

operation

If skip and followed by 2-word instruction:

operation

Example:

HERE DCFSNZ TEMP, 1, 0

ZERO :

NZERO :

Before Instruction

TEMP

After Instruction

TEMP

TEMP - 1,

If TEMP

PC =

Address (ZERO)

If TEMP

PC =

Address (NZERO)

2003 Microchip Technology Inc.

Advance Information

DS39609A-page 281

PIC18FXX20

INCFSZ

Increment f, skip if 0

Syntax:

[ label ] INCFSZ f [,d [,a]

Operands:

f 255

[0,1]

Operation:

(f) + 1

dest,

skip if result = 0

Status Affected:

None

Encoding:

0011

11da

ffff

Description:

The contents of register 'f' are
incremented. If 'd' is 0, the result is
placed in W. If 'd' is 1, the result is
placed back in register 'f'. (default)
If the result is 0, the next instruc-
tion, which is already fetched, is
discarded, and a NOP is executed
instead, making it a two-cycle
instruction. If `a' is 0, the Access
Bank will be selected, overriding
the BSR value. If `a' = 1, then the
bank will be selected as per the
BSR value (default).

Words:

Cycles:

1(2)
Note: 3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Decode

Read

Process

Data

Write to

destination

If skip:

operation

If skip and followed by 2-word instruction:

operation

Example:

HERE INCFSZ CNT, 1, 0
NZERO :
ZERO :

Before Instruction

PC =

Address (HERE)

After Instruction

CNT

CNT + 1

If CNT

= Address (ZERO)

If CNT

PC =

Address (NZERO)

INFSNZ

Increment f, skip if not 0

Syntax:

[label] INFSNZ f [,d [,a]

Operands:

f 255

[0,1]

Operation:

(f) + 1

dest,

skip if result

Status Affected:

None

Encoding:

0100

10da

ffff

Description:

The contents of register 'f' are
incremented. If 'd' is 0, the result is
placed in W. If 'd' is 1, the result is
placed back in register 'f' (default).
If the result is not 0, the next
instruction, which is already
fetched, is discarded, and a NOP is
executed instead, making it a
two-cycle instruction. If `a' is 0, the
Access Bank will be selected, over-
riding the BSR value. If `a' = 1, then
the bank will be selected as per the
BSR value (default).

Words:

Cycles:

1(2)
Note: 3 cycles if skip and followed

by a 2-word instruction.

Q Cycle Activity:

Decode

Read

Process

Data

Write to

destination

If skip:

operation

If skip and followed by 2-word instruction:

operation

Example:

HERE INFSNZ REG, 1, 0
ZERO
NZERO

Before Instruction

PC =

Address (HERE)

After Instruction

REG

REG + 1

If REG

PC =

Address (NZERO)

If REG

PC =

Address (ZERO)

PIC18FXX20

DS39609A-page 286

Advance Information

2003 Microchip Technology Inc.

MULLW

Multiply Literal with W

Syntax:

[ label ] MULLW k

Operands:

k 255

Operation:

(W) x k

PRODH:PRODL

Status Affected:

None

Encoding:

0000

1101

kkkk

Description:

An unsigned multiplication is car-
ried out between the contents of
W and the 8-bit literal 'k'. The
16-bit result is placed in
PRODH:PRODL register pair.
PRODH contains the high byte.
W is unchanged.
None of the status flags are
affected.
Note that neither overflow nor
carry is possible in this opera-
tion. A zero result is possible but
not detected.

Words:

Cycles:

Q Cycle Activity:

Decode

Read

literal 'k'

Process

Data

Write

registers
PRODH:

PRODL

Example:

MULLW 0xC4

Before Instruction

0xE2

PRODH

PRODL

After Instruction

0xE2

PRODH

0xAD

PRODL

0x08

MULWF

Multiply W with f

Syntax:

[ label ] MULWF f [,a]

Operands:

f 255

[0,1]

Operation:

(W) x (f)

PRODH:PRODL

Status Affected:

None

Encoding:

0000

001a

ffff

Description:

An unsigned multiplication is car-
ried out between the contents of
W and the register file location 'f'.
The 16-bit result is stored in the
PRODH:PRODL register pair.
PRODH contains the high byte.
Both W and 'f' are unchanged.
None of the status flags are
affected.
Note that neither overflow nor
carry is possible in this opera-
tion. A zero result is possible but
not detected. If `a' is 0, the
Access Bank will be selected,
overriding the BSR value. If
`a'= 1, then the bank will be
selected as per the BSR value
(default).

Words:

Cycles:

Q Cycle Activity:

Decode

Read

Process

Data

Write

registers
PRODH:

PRODL

Example:

MULWF REG, 1

Before Instruction

0xC4

REG

0xB5

PRODH

PRODL

After Instruction

0xC4

REG

0xB5

PRODH

0x8A

PRODL

0x94

PIC18FXX20

DS39609A-page 290

Advance Information

2003 Microchip Technology Inc.

RETFIE

Return from Interrupt

Syntax:

[ label ] RETFIE [s]

Operands:

[0,1]

Operation:

(TOS)

PC,

GIE/GIEH or PEIE/GIEL,

if s = 1
(WS)

(STATUSS)

STATUS,

(BSRS)

BSR,

PCLATU, PCLATH are unchanged.

Status Affected:

GIE/GIEH, PEIE/GIEL.

Encoding:

0000

0001

000s

Description:

Return from Interrupt. Stack is
popped and Top-of-Stack (TOS) is
loaded into the PC. Interrupts are
enabled by setting either the high
or low priority global interrupt
enable bit. If `s' = 1, the contents of
the shadow registers WS,
STATUSS and BSRS are loaded
into their corresponding registers,
W, STATUS and BSR. If `s' = 0, no
update of these registers occurs
(default).

Words:

Cycles:

Q Cycle Activity:

Decode

operation

pop PC from

stack

Set GIEH or

GIEL

operation

Example:

RETFIE 1

After Interrupt

TOS

BSR

BSRS

STATUS

STATUSS

GIE/GIEH, PEIE/GIEL

RETLW

Return Literal to W

Syntax:

[ label ] RETLW k

Operands:

k 255

Operation:

(TOS)

PC,

PCLATU, PCLATH are unchanged

Status Affected:

None

Encoding:

0000

1100

kkkk

Description:

W is loaded with the eight-bit literal
'k'. The program counter is loaded
from the top of the stack (the return
address). The high address latch
(PCLATH) remains unchanged.

Words:

Cycles:

Q Cycle Activity:

Decode

Read

literal 'k'

Process

Data

pop PC from

stack, Write

to W

operation

Example:

CALL TABLE ; W contains table

; offset value

; W now has

; table value

TABLE

ADDWF PCL

; W = offset

RETLW k0

; Begin table

RETLW k1

;

RETLW kn

; End of table

Before Instruction

0x07

After Instruction

value of kn

PIC18FXX20

DS39609A-page 294

Advance Information

2003 Microchip Technology Inc.

SLEEP

Enter SLEEP mode

Syntax:

[ label ] SLEEP

Operands:

None

Operation:

00h

WDT,

WDT postscaler,

TO,

Status Affected:

TO, PD

Encoding:

0000

0011

Description:

The power-down status bit (PD) is
cleared. The time-out status bit
(TO) is set. Watchdog Timer and
its postscaler are cleared.
The processor is put into SLEEP
mode with the oscillator stopped.

Words:

Cycles:

Q Cycle Activity:

Decode

operation

Process

Data

Go to
sleep

Example:

SLEEP

Before Instruction

TO =

PD =

After Instruction

TO =

PD =

If WDT causes wake-up, this bit is cleared.

SUBFWB

Subtract f from W with borrow

Syntax:

[ label ] SUBFWB f [,d [,a]

Operands:

f 255

[0,1]

Operation:

(W) � (f) � (C)

dest

Status Affected:

N, OV, C, DC, Z

Encoding:

0101

01da

ffff

Description:

Subtract register 'f' and carry flag
(borrow) from W (2's complement
method). If 'd' is 0, the result is
stored in W. If 'd' is 1, the result is
stored in register 'f' (default). If `a' is
0, the Access Bank will be selected,
overriding the BSR value. If `a' is 1,
then the bank will be selected as
per the BSR value (default).

Words:

Cycles:

Q Cycle Activity:

Decode

Read

Process

Data

Write to

destination

Example 1:

SUBFWB REG, 1, 0

Before Instruction

REG

After Instruction

REG

1 ; result is negative

Example 2:

SUBFWB REG, 0, 0

Before Instruction

REG

After Instruction

REG

0 ; result is positive

Example 3:

SUBFWB REG, 1, 0

Before Instruction

REG

After Instruction

REG

1 ; result is zero

2003 Microchip Technology Inc.

Advance Information

DS39609A-page 295

PIC18FXX20

SUBLW

Subtract W from literal

Syntax:

[ label ] SUBLW k

Operands:

k 255

Operation:

k � (W)

Status Affected:

N, OV, C, DC, Z

Encoding:

0000

1000

kkkk

Description:

W is subtracted from the eight-bit
literal 'k'. The result is placed in
W.

Words:

Cycles:

Q Cycle Activity:

Decode

Read

literal 'k'

Process

Data

Write to W

Example 1:

SUBLW

0x02

Before Instruction

After Instruction

1 ; result is positive

Example 2:

SUBLW

0x02

Before Instruction

After Instruction

1 ; result is zero

Example 3:

SUBLW

0x02

Before Instruction

After Instruction

FF ; (2's complement)

0 ; result is negative

SUBWF

Subtract W from f

Syntax:

[ label ] SUBWF f [,d [,a]

Operands:

f 255

[0,1]

Operation:

(f) � (W)

dest

Status Affected:

N, OV, C, DC, Z

Encoding:

0101

11da

ffff

Description:

Subtract W from register 'f' (2's
complement method). If 'd' is 0,
the result is stored in W. If 'd' is 1,
the result is stored back in regis-
ter 'f' (default). If `a' is 0, the
Access Bank will be selected,
overriding the BSR value. If `a' is
1, then the bank will be selected
as per the BSR value (default).

Words:

Cycles:

Q Cycle Activity:

Decode

Read

Process

Data

Write to

destination

Example 1:

SUBWF REG, 1, 0

Before Instruction

REG

After Instruction

REG

1 ; result is positive

Example 2:

SUBWF REG, 0, 0

Before Instruction

REG

After Instruction

REG

1 ; result is zero

Example 3:

SUBWF REG, 1, 0

Before Instruction

REG

After Instruction

REG

FFh ;(2's complement)

0 ; result is negative

PIC18FXX20

DS39609A-page 296

Advance Information

2003 Microchip Technology Inc.

SUBWFB

Subtract W from f with Borrow

Syntax:

[ label ] SUBWFB f [,d [,a]

Operands:

f 255

[0,1]

Operation:

(f) � (W) � (C)

dest

Status Affected:

N, OV, C, DC, Z

Encoding:

0101

10da

ffff

Description:

Subtract W and the carry flag (bor-
row) from register 'f' (2's complement
method). If 'd' is 0, the result is stored
in W. If 'd' is 1, the result is stored
back in register 'f' (default). If `a' is 0,
the Access Bank will be selected,
overriding the BSR value. If `a' is 1,
then the bank will be selected as per
the BSR value (default).

Words:

Cycles:

Q Cycle Activity:

Decode

Read

Process

Data

Write to

destination

Example 1:

SUBWFB REG, 1, 0

Before Instruction

REG

0x19

(0001 1001)

0x0D

(0000 1101)

After Instruction

REG

0x0C

(0000 1011)

0x0D

(0000 1101)

; result is positive

Example 2:

SUBWFB

REG, 0, 0

Before Instruction

REG

0x1B

(0001 1011)

0x1A

(0001 1010)

After Instruction

REG

0x1B

(0001 1011)

0x00

; result is zero

Example 3:

SUBWFB REG, 1, 0

Before Instruction

REG

0x03

(0000 0011)

0x0E

(0000 1101)

After Instruction

REG

0xF5

(1111 0100)

; [2's comp]

0x0E

(0000 1101)

; result is negative

SWAPF

Swap f

Syntax:

[ label ] SWAPF f [,d [,a]

Operands:

f 255

[0,1]

Operation:

(f<3:0>)

dest<7:4>,

(f<7:4>)

dest<3:0>

Status Affected:

None

Encoding:

0011

10da

ffff

Description:

The upper and lower nibbles of reg-
ister 'f' are exchanged. If 'd' is 0, the
result is placed in W. If 'd' is 1, the
result is placed in register 'f'
(default). If `a' is 0, the Access
Bank will be selected, overriding
the BSR value. If `a' is 1, then the
bank will be selected as per the
BSR value (default).

Words:

Cycles:

Q Cycle Activity:

Decode

Read

Process

Data

Write to

destination

Example:

SWAPF

REG, 1, 0

Before Instruction

REG

0x53

After Instruction

REG

0x35

PIC18FXX20

DS39609A-page 298

Advance Information

2003 Microchip Technology Inc.

TBLWT Table

Write

Syntax:

[ label ] TBLWT ( *; *+; *-; +*)

Operands:

None

Operation:

if TBLWT*,

(TABLAT)

Holding Register;

TBLPTR - No Change;

if TBLWT*+,

(TABLAT)

Holding Register;

(TBLPTR) +1

TBLPTR;

if TBLWT*-,

(TABLAT)

Holding Register;

(TBLPTR) -1

TBLPTR;

if TBLWT+*,

(TBLPTR) +1

TBLPTR;

(TABLAT)

Holding Register;

Status Affected: None
Encoding:

0000

11nn

nn=0 *

=1 *+

=2 *-

=3 +*

Description:

This instruction uses the 3 LSBs of
TBLPTR to determine which of the 8
holding registers the TABLAT is writ-
ten to. The holding registers are used
to program the contents of Program
Memory (P.M.). (Refer to Section 5.0
for additional details on programming
FLASH memory.)
The TBLPTR (a 21-bit pointer) points
to each byte in the program memory.
TBLPTR has a 2-MByte address
range. The LSb of the TBLPTR
selects which byte of the program
memory location to access.

TBLPTR[0] = 0:Least Significant

Byte of Program
Memory Word

TBLPTR[0] = 1:Most Significant

Byte of Program
Memory Word

The TBLWT instruction can modify
the value of TBLPTR as follows:
� no change
� post-increment
� post-decrement
� pre-increment

TBLWT Table Write (Continued)

Words: 1
Cycles: 2
Q Cycle Activity:

Decode

operation

(Read

TABLAT)

operation

(Write to

Holding

Example1:

TBLWT *+;

Before Instruction

TABLAT =

0x55

TBLPTR

0x00A356

HOLDING REGISTER

(0x00A356)

0xFF

After Instructions (table write completion)

TABLAT

0x55

TBLPTR

0x00A357

HOLDING REGISTER

(0x00A356)

0x55

Example 2:

TBLWT +*;

Before Instruction

TABLAT

0x34

TBLPTR

0x01389A

HOLDING REGISTER

(0x01389A)

0xFF

HOLDING REGISTER

(0x01389B)

0xFF

After Instruction (table write completion)

TABLAT

0x34

TBLPTR

0x01389B

HOLDING REGISTER

(0x01389A)

0xFF

HOLDING REGISTER

(0x01389B)

0x34

2003 Microchip Technology Inc.

Advance Information

DS39609A-page 301

PIC18FXX20

25.0 DEVELOPMENT SUPPORT

The PICmicro

�

microcontrollers are supported with a

full range of hardware and software development tools:
� Integrated Development Environment

- MPLAB

�

IDE Software

� Assemblers/Compilers/Linkers

- MPASM

Assembler

- MPLAB C17 and MPLAB C18 C Compilers
- MPLINK

Object Linker/

MPLIB

Object Librarian

- MPLAB C30 C Compiler
- MPLAB ASM30 Assembler/Linker/Library

� Simulators

- MPLAB SIM Software Simulator
- MPLAB dsPIC30 Software Simulator

� Emulators

- MPLAB ICE 2000 In-Circuit Emulator
- MPLAB ICE 4000 In-Circuit Emulator

� In-Circuit Debugger

- MPLAB ICD 2

� Device Programmers

- PRO MATE

�

II Universal Device Programmer

- PICSTART

�

Plus Development Programmer

� Low Cost Demonstration Boards

- PICDEM

1 Demonstration Board

- PICDEM.net

Demonstration Board

- PICDEM 2 Plus Demonstration Board
- PICDEM 3 Demonstration Board
- PICDEM 17 Demonstration Board
- PICDEM 18R Demonstration Board
- PICDEM LIN Demonstration Board
- PICDEM USB Demonstration Board

� Evaluation Kits

- K

�

- PICDEM MSC
- microID

�

- CAN
- PowerSmart

�

- Analog

25.1

MPLAB Integrated Development
Environment Software

The MPLAB IDE software brings an ease of software
development previously unseen in the 8/16-bit micro-
controller market. The MPLAB IDE is a Windows

�

based application that contains:
� An interface to debugging tools

- simulator
- programmer (sold separately)
- emulator (sold separately)
- in-circuit debugger (sold separately)

� A full-featured editor with color coded context
� A multiple project manager
� Customizable data windows with direct edit of

contents

� High level source code debugging
� Mouse over variable inspection
� Extensive on-line help
The MPLAB IDE allows you to:
� Edit your source files (either assembly or C)
� One touch assemble (or compile) and download

to PICmicro emulator and simulator tools
(automatically updates all project information)

� Debug using:

- source files (assembly or C)
- absolute listing file (mixed assembly and C)
- machine code

MPLAB IDE supports multiple debugging tools in a
single development paradigm, from the cost effective
simulators, through low cost in-circuit debuggers, to
full-featured emulators. This eliminates the learning
curve when upgrading to tools with increasing flexibility
and power.

25.2

MPASM Assembler

The MPASM assembler is a full-featured, universal
macro assembler for all PICmicro MCUs.
The MPASM assembler generates relocatable object
files for the MPLINK object linker, Intel

�

standard HEX

files, MAP files to detail memory usage and symbol ref-
erence, absolute LST files that contains source lines
and generated machine code and COFF files for
debugging.
The MPASM assembler features include:
� Integration into MPLAB IDE projects
� User defined macros to streamline assembly code
� Conditional assembly for multi-purpose source files
� Directives that allow complete control over the

assembly process

PIC18FXX20

DS39609A-page 302

Advance Information

2003 Microchip Technology Inc.

25.3

MPLAB C17 and MPLAB C18
C Compilers

The MPLAB C17 and MPLAB C18 Code Development
Systems are complete ANSI C compilers for
Microchip's PIC17CXXX and PIC18CXXX family of
microcontrollers. These compilers provide powerful
integration capabilities, superior code optimization and
ease of use not found with other compilers.
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.

25.4

MPLINK Object Linker/
MPLIB Object Librarian

The MPLINK object linker combines relocatable
objects created by the MPASM assembler and the
MPLAB C17 and MPLAB C18 C compilers. It can link
relocatable objects from pre-compiled libraries, using
directives from a linker script.
The MPLIB object librarian manages the creation and
modification of library files of pre-compiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
The object linker/library features include:
� Efficient linking of single libraries instead of many

smaller files

� Enhanced code maintainability by grouping

related modules together

� Flexible creation of libraries with easy module

listing, replacement, deletion and extraction

25.5

MPLAB C30 C Compiler

The MPLAB C30 C compiler is a full-featured, ANSI
compliant, optimizing compiler that translates standard
ANSI C programs into dsPIC30F assembly language
source. The compiler also supports many command-
line options and language extensions to take full
advantage of the dsPIC30F device hardware capabili-
ties, and afford fine control of the compiler code
generator.
MPLAB C30 is distributed with a complete ANSI C
standard library. All library functions have been vali-
dated and conform to the ANSI C library standard. The
library includes functions for string manipulation,
dynamic memory allocation, data conversion, time-
keeping, and math functions (trigonometric, exponen-
tial and hyperbolic). The compiler provides symbolic
information for high level source debugging with the
MPLAB IDE.

25.6

MPLAB ASM30 Assembler, Linker,
and Librarian

MPLAB ASM30 assembler produces relocatable
machine code from symbolic assembly language for
dsPIC30F devices. MPLAB C30 compiler uses the
assembler to produce it's object file. The assembler
generates relocatable object files that can then be
archived or linked with other relocatable object files and
archives to create an executable file. Notable features
of the assembler include:
� Support for the entire dsPIC30F instruction set
� Support for fixed-point and floating-point data
� Command line interface
� Rich directive set
� Flexible macro language
� MPLAB IDE compatibility

25.7

MPLAB SIM Software Simulator

The MPLAB SIM software simulator allows code devel-
opment in a PC hosted environment by simulating the
PICmicro series microcontrollers on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a file, or user defined key press, to any pin. The execu-
tion can be performed in Single-Step, Execute Until
Break, or Trace mode.
The MPLAB SIM simulator fully supports symbolic
debugging using the MPLAB C17 and MPLAB C18
C Compilers, as well as the MPASM assembler. The
software simulator offers the flexibility to develop and
debug code outside of the laboratory environment,
making it an excellent, economical software
development tool.

25.8

MPLAB SIM30 Software Simulator

The MPLAB SIM30 software simulator allows code
development in a PC hosted environment by simulating
the dsPIC30F series microcontrollers on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a file, or user defined key press, to any of the pins.
The MPLAB SIM30 simulator fully supports symbolic
debugging using the MPLAB C30 C Compiler and
MPLAB ASM30 assembler. The simulator runs in either
a Command Line mode for automated tasks, or from
MPLAB IDE. This high speed simulator is designed to
debug, analyze and optimize time intensive DSP
routines.

2003 Microchip Technology Inc.

Advance Information

DS39609A-page 303

PIC18FXX20

25.9

MPLAB ICE 2000
High Performance Universal
In-Circuit Emulator

The MPLAB ICE 2000 universal in-circuit emulator is
intended to provide the product development engineer
with a complete microcontroller design tool set for
PICmicro microcontrollers. Software control of the
MPLAB ICE 2000 in-circuit emulator is advanced by
the MPLAB Integrated Development Environment,
which allows editing, building, downloading and source
debugging from a single environment.
The MPLAB ICE 2000 is a full-featured emulator sys-
tem with enhanced trace, trigger and data monitoring
features. Interchangeable processor modules allow the
system to be easily reconfigured for emulation of differ-
ent processors. The universal architecture of the
MPLAB ICE in-circuit emulator allows expansion to
support new PICmicro microcontrollers.
The MPLAB ICE 2000 in-circuit emulator system has
been designed as a real-time emulation system with
advanced features that are typically found on more
expensive development tools. The PC platform and
Microsoft

�

Windows 32-bit operating system were

chosen to best make these features available in a
simple, unified application.

25.10 MPLAB ICE 4000

High Performance Universal
In-Circuit Emulator

The MPLAB ICE 4000 universal in-circuit emulator is
intended to provide the product development engineer
with a complete microcontroller design tool set for high-
end PICmicro microcontrollers. Software control of the
MPLAB ICE in-circuit emulator is provided by the
MPLAB Integrated Development Environment, which
allows editing, building, downloading and source
debugging from a single environment.
The MPLAB ICD 4000 is a premium emulator system,
providing the features of MPLAB ICE 2000, but with
increased emulation memory and high speed perfor-
mance for dsPIC30F and PIC18XXXX devices. Its
advanced emulator features include complex triggering
and timing, up to 2 Mb of emulation memory, and the
ability to view variables in real-time.
The MPLAB ICE 4000 in-circuit emulator system has
been designed as a real-time emulation system with
advanced features that are typically found on more
expensive development tools. The PC platform and
Microsoft Windows 32-bit operating system were cho-
sen to best make these features available in a simple,
unified application.

25.11 MPLAB ICD 2 In-Circuit Debugger

Microchip's In-Circuit Debugger, MPLAB ICD 2, is a
powerful, low cost, run-time development tool,
connecting to the host PC via an RS-232 or high speed
USB interface. This tool is based on the FLASH
PICmicro MCUs and can be used to develop for these
and other PICmicro microcontrollers. The MPLAB
ICD 2 utilizes the in-circuit debugging capability built
into the FLASH devices. This feature, along with
Microchip's In-Circuit Serial Programming

(ICSP

)

protocol, offers cost effective in-circuit FLASH debug-
ging from the graphical user interface of the MPLAB
Integrated Development Environment. This enables a
designer to develop and debug source code by setting
breakpoints, single-stepping and watching variables,
CPU status and peripheral registers. Running at full
speed enables testing hardware and applications in
real-time. MPLAB ICD 2 also serves as a development
programmer for selected PICmicro devices.

25.12 PRO MATE II Universal Device

Programmer

The PRO MATE II is a universal, CE compliant device
programmer with programmable voltage verification at
V

DDMIN

and V

DDMAX

for maximum reliability. It features

an LCD display for instructions and error messages
and a modular detachable socket assembly to support
various package types. In Stand-Alone mode, the
PRO MATE II device programmer can read, verify, and
program PICmicro devices without a PC connection. It
can also set code protection in this mode.

25.13 PICSTART Plus Development

Programmer

The PICSTART Plus development programmer is an
easy-to-use, low cost, prototype programmer. It con-
nects to the PC via a COM (RS-232) port. MPLAB
Integrated Development Environment software makes
using the programmer simple and efficient. The
PICSTART Plus development programmer supports
most PICmicro devices up to 40 pins. Larger pin count
devices, such as the PIC16C92X and PIC17C76X,
may be supported with an adapter socket. The
PICSTART Plus development programmer is CE
compliant.

PIC18FXX20

DS39609A-page 304

Advance Information

2003 Microchip Technology Inc.

25.14 PICDEM 1 PICmicro

Demonstration Board

The PICDEM 1 demonstration board demonstrates the
capabilities of the PIC16C5X (PIC16C54 to
PIC16C58A), PIC16C61, PIC16C62X, PIC16C71,
PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. All
necessary hardware and software is included to run
basic demo programs. The sample microcontrollers
provided with the PICDEM 1 demonstration board can
be programmed with a PRO MATE II device program-
mer, or a PICSTART Plus development programmer.
The PICDEM 1 demonstration board can be connected
to the MPLAB ICE in-circuit emulator for testing. A pro-
totype area extends the circuitry for additional applica-
tion components. Features include an RS-232
interface, a potentiometer for simulated analog input,
push button switches and eight LEDs.

25.15 PICDEM.net Internet/Ethernet

Demonstration Board

The PICDEM.net demonstration board is an Internet/
Ethernet demonstration board using the PIC18F452
microcontroller and TCP/IP firmware. The board
supports any 40-pin DIP device that conforms to the
standard pinout used by the PIC16F877 or
PIC18C452. This kit features a user friendly TCP/IP
stack, web server with HTML, a 24L256 Serial
EEPROM for Xmodem download to web pages into
Serial EEPROM, ICSP/MPLAB ICD 2 interface con-
nector, an Ethernet interface, RS-232 interface, and a
16 x 2 LCD display. Also included is the book and
CD-ROM "TCP/IP Lean, Web Servers for Embedded
Systems," by Jeremy Bentham

25.16 PICDEM 2 Plus

Demonstration Board

The PICDEM 2 Plus demonstration board supports
many 18-, 28-, and 40-pin microcontrollers, including
PIC16F87X and PIC18FXX2 devices. All the neces-
sary hardware and software is included to run the dem-
onstration programs. The sample microcontrollers
provided with the PICDEM 2 demonstration board can
be programmed with a PRO MATE II device program-
mer, PICSTART Plus development programmer, or
MPLAB ICD 2 with a Universal Programmer Adapter.
The MPLAB ICD 2 and MPLAB ICE in-circuit emulators
may also be used with the PICDEM 2 demonstration
board to test firmware. A prototype area extends the
circuitry for additional application components. Some
of the features include an RS-232 interface, a 2 x 16
LCD display, a piezo speaker, an on-board temperature
sensor, four LEDs, and sample PIC18F452 and
PIC16F877 FLASH microcontrollers.

25.17 PICDEM 3 PIC16C92X

Demonstration Board

The PICDEM 3 demonstration board supports the
PIC16C923 and PIC16C924 in the PLCC package. All
the necessary hardware and software is included to run
the demonstration programs.

25.18 PICDEM 17 Demonstration Board

The PICDEM 17 demonstration board is an evaluation
board that demonstrates the capabilities of several
Microchip microcontrollers, including PIC17C752,
PIC17C756A, PIC17C762 and PIC17C766. A pro-
grammed sample is included. The PRO MATE II device
programmer, or the PICSTART Plus development pro-
grammer, can be used to reprogram the device for user
tailored application development. The PICDEM 17
demonstration board supports program download and
execution from external on-board FLASH memory. A
generous prototype area is available for user hardware
expansion.

2003 Microchip Technology Inc.

Advance Information

DS39609A-page 305

PIC18FXX20

25.19 PICDEM 18R PIC18C601/801

Demonstration Board

The PICDEM 18R demonstration board serves to assist
development of the PIC18C601/801 family of Microchip
microcontrollers. It provides hardware implementation
of both 8-bit Multiplexed/De-multiplexed and 16-bit
Memory modes. The board includes 2 Mb external
FLASH memory and 128 Kb SRAM memory, as well as
serial EEPROM, allowing access to the wide range of
memory types supported by the PIC18C601/801.

25.20 PICDEM LIN PIC16C43X

Demonstration Board

The powerful LIN hardware and software kit includes a
series of boards and three PICmicro microcontrollers.
The small footprint PIC16C432 and PIC16C433 are
used as slaves in the LIN communication and feature
on-board LIN transceivers. A PIC16F874 FLASH
microcontroller serves as the master. All three micro-
controllers are programmed with firmware to provide
LIN bus communication.

25.21 PICDEM USB PIC16C7X5

Demonstration Board

The PICDEM USB Demonstration Board shows off the
capabilities of the PIC16C745 and PIC16C765 USB
microcontrollers. This board provides the basis for
future USB products.

25.22 Evaluation and

Programming Tools

In addition to the PICDEM series of circuits, Microchip
has a line of evaluation kits and demonstration software
for these products.
� K

evaluation and programming tools for

Microchip's HCS Secure Data Products

� CAN developers kit for automotive network

applications

� Analog design boards and filter design software
� PowerSmart battery charging evaluation/

calibration kits

� IrDA

�

development kit

� microID development and RFLab

development

software

� SEEVAL

�

designer kit for memory evaluation and

endurance calculations

� PICDEM MSC demo boards for Switching mode

power supply, high power IR driver, delta sigma
ADC, and flow rate sensor

Check the Microchip web page and the latest Product
Line Card for the complete list of demonstration and
evaluation kits.

PIC18FXX20

DS39609A-page 306

Advance Information

2003 Microchip Technology Inc.

TABLE 25-1:

DEVELOPMENT TOOLS FROM MICROCHIP

PIC

12C

XXX

PIC1

XXX

PIC

140

PIC1

PIC

16C

XXX

PIC

16C

43X

PIC

16F

62X

PIC1

PIC

16C

7X5

PIC1

PIC

16F

8XX

PIC1

XX2

PI1

8CX0

PIC1

XXX

dsPI

ftwa

ols

e
v

e
lo

t E

r
o

AB C1

C Co

e
r

AB C1

C Co

e
r

ASM

e
m

r
/

I
N

ct L

i
n

k
e

AB C3

C Co

e
r

AB ASM

s
s

e
mb

l
e
r/

i
n

k
e

r
/
L

i
b

a
n

Emu

lat

ors

AB ICE 2

0
0
0

-Cir

l
a

t
o

AB ICE 4

0
0
0

-Cir

it E

l
at

bugg

AB ICD

2 In

-Cir

e
bu

gge

Programmers

PICST

ART

Ent

r
y
Le

e
l

e
v

e
l
o

e
n

t
Pr

mme

O M

i
ver

l D

vic

e
P

r
og

r
a

ard

s an

d E

val K

its

PICDEM

s
t
r
a
t
i
o

r
d

PICDEM

.
n

e
t
De

t
r
a
t
io

r
d

PICDEM

Plu

s
De

s
t
r
a
t
io

r
d

PICDEM

s
t
r
a
t
i
o

r
d

PICDEM

4
A D

e
m

s
t
r
a

t
io

r
d

PICDEM

7
De

s
t
r
a

t
io

r
d

PICDEM

8
R D

e
m

s
t
r
a

t
io

r
d

PICDEM

I
N D

e
m

s
t
r
a

t
io

r
d

PICDEM

s
t
r
a

t
io

r
d

n
tact

the

ochi

e
b

.mi

c
r
o
ch

i
p

.co

r i

for

t
i
on

how

to u

s
e t

In-

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r
cu

i
t
D

e
b

ugg

1
6

4
0

01)

i
t
h

I
C

1
6

62,

63,

, 65

, 7

2
, 7

3
, 7

4
,

76,

77.

*
*

n
t
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c
t M

i
cr

c
h
i
p

T
e
ch

n
o

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y
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r

a
v
a

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ility d

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t
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ent

too

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is av

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l
e

sele

ct d

e
vice

2003 Microchip Technology Inc.

Advance Information

DS39609A-page 307

PIC18FXX20

26.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings

()

Ambient temperature under bias.............................................................................................................-55癈 to +125癈
Storage temperature .............................................................................................................................. -65癈 to +150癈
Voltage on any pin with respect to V

(except V

, MCLR, and RA4) ......................................... -0.3V to (V

+ 0.3V)

Voltage on V

with respect to V

......................................................................................................... -0.3V to +5.5V

Voltage on MCLR with respect to V

(Note 2) ......................................................................................... 0V to +13.25V

Voltage on RA4 with respect to Vss ............................................................................................................. 0V to +12.0V
Total power dissipation (Note 1) ...............................................................................................................................1.0W
Maximum current out of V

pin ...........................................................................................................................300 mA

Maximum current into V

pin ..............................................................................................................................250 mA

Input clamp current, I

< 0 or V

> V

)

...................................................................................................................... �20 mA

Output clamp current, I

< 0 or V

> V

)

.............................................................................................................. �20 mA

Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................25 mA
Maximum current sunk by

all ports .......................................................................................................................200 mA

Maximum current sourced by all ports ..................................................................................................................200 mA

Note 1: Power dissipation is calculated as follows:

Pdis = V

x {I

} +

{(V

-V

) x I

} +

l x I

)

2: Voltage spikes below V

at the MCLR/V

pin, inducing currents greater than 80 mA, may cause latchup.

Thus, a series resistor of 50-100

should be used when applying a "low" level to the MCLR/V

pin, rather

than pulling this pin directly to V

NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.

2003 Microchip Technology Inc.

Advance Information

DS39609A-page 311

PIC18FXX20

26.2

DC Characteristics: Power-down and Supply Current

PIC18FXX20 (Industrial, Extended)
PIC18LFXX20 (Industrial)

PIC18LFXX20
(Industrial)

Standard Operating Conditions (unless otherwise stated)
Operating temperature

-40癈

+85癈 for industrial

PIC18FXX20
(Industrial, Extended)

Standard Operating Conditions (unless otherwise stated)
Operating temperature

-40癈

+85癈 for industrial

-40癈

+125癈 for extended

Param

No.

Device

Typ

Max

Units

Conditions

Power-down Current (I

)

(1)

PIC18LFXX20

0.2

礎

-40癈

= 2.0V,

(SLEEP mode)

0.2

礎

25癈

1.2

礎

85癈

PIC18LFXX20

0.4

礎

-40癈

= 3.0V,

(SLEEP mode)

0.4

礎

25癈

1.8

礎

85癈

All devices

0.7

礎

-40癈

= 5.0V,

(SLEEP mode)

0.7

礎

25癈

3.0

礎

85癈

Legend: Shading of rows is to assist in readability of the table.
Note 1: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with

the part in SLEEP mode, with all I/O pins in high-impedance state and tied to V

or V

, and all features that add delta

current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).

2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading

and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the
current consumption.
The test conditions for all I

measurements in active Operation mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to V

;

MCLR = V

; WDT enabled/disabled as specified.

3: For RC oscillator configurations, current through R

EXT

is not included. The current through the resistor can be estimated

by the formula Ir = V

/2R

EXT

(mA) with R

EXT

in k

PIC18FXX20

DS39609A-page 312

Advance Information

2003 Microchip Technology Inc.

Supply Current (I

)

(2,3)

PIC18LFXX20

165

350

礎

-40癈

OSC

= 1 MH

EC oscillator

165

350

礎

25癈 V

= 2.0V

170

350

礎

85癈

PIC18LFXX20

360

750

礎

-40癈

340

750

礎

25癈

= 3.0V

300

750

礎

85癈

All devices

800

1700

礎

-40癈

730

1700

礎

25癈

= 5.0V

700

1700

礎

85癈

PIC18LFXX20

600

1200

礎

-40癈

OSC

= 4 MHz,

EC oscillator

600

1200

礎

25癈 V

= 2.0V

640

1300

礎

85癈

PIC18LFXX20 1000

2500

礎

-40癈

1000

2500

礎

25癈

= 3.0V

1000

2500

礎

85癈

All devices

2.2

5.0

-40癈

2.1

5.0

25癈

= 5.0V

2.0

5.0

85癈

26.2

DC Characteristics: Power-down and Supply Current

PIC18FXX20 (Industrial, Extended)
PIC18LFXX20 (Industrial) (Continued)

PIC18LFXX20
(Industrial)

Standard Operating Conditions (unless otherwise stated)
Operating temperature

-40癈

+85癈 for industrial

PIC18FXX20
(Industrial, Extended)

Standard Operating Conditions (unless otherwise stated)
Operating temperature

-40癈

+85癈 for industrial

-40癈

+125癈 for extended

Param

No.

Device

Typ

Max

Units

Conditions

Legend: Shading of rows is to assist in readability of the table.
Note 1: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with

the part in SLEEP mode, with all I/O pins in high-impedance state and tied to V

or V

, and all features that add delta

current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).

2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading

and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the
current consumption.
The test conditions for all I

measurements in active Operation mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to V

;

MCLR = V

; WDT enabled/disabled as specified.

3: For RC oscillator configurations, current through R

EXT

is not included. The current through the resistor can be estimated

by the formula Ir = V

/2R

EXT

(mA) with R

EXT

in k

2003 Microchip Technology Inc.

Advance Information

DS39609A-page 313

PIC18FXX20

Supply Current (I

)

(2,3)

PIC18FX620,

PIC18FX720

9.3

-40癈

OSC

= 25 MH

EC oscillator

9.5

25癈

= 4.2V

85癈

PIC18FX620,

PIC18FX720

11.8

-40癈

25癈

= 5.0V

85癈

PIC18FX520 TBD

TBD

-40癈

OSC

= 40 MH

EC oscillator

TBD

25癈

= 4.2V

TBD

85癈

PIC18FX520 TBD

TBD

-40癈

TBD

25癈

= 5.0V

TBD

85癈

PIC18LFXX20 TBD

TBD

礎

-10癈

OSC

= 32 kHz,

Timer1 as clock

TBD

礎

25癈 V

= 2.0V

TBD

礎

70癈

PIC18LFXX20 TBD

TBD

礎

-10癈

TBD

礎

25癈

= 3.0V

TBD

礎

70癈

All devices TBD

TBD

礎

-10癈

TBD

礎

25癈

= 5.0V

TBD

礎

70癈

26.2

DC Characteristics: Power-down and Supply Current

PIC18FXX20 (Industrial, Extended)
PIC18LFXX20 (Industrial) (Continued)

PIC18LFXX20
(Industrial)

Standard Operating Conditions (unless otherwise stated)
Operating temperature

-40癈

+85癈 for industrial

PIC18FXX20
(Industrial, Extended)

Standard Operating Conditions (unless otherwise stated)
Operating temperature

-40癈

+85癈 for industrial

-40癈

+125癈 for extended

Param

No.

Device

Typ

Max

Units

Conditions

Legend: Shading of rows is to assist in readability of the table.
Note 1: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with

the part in SLEEP mode, with all I/O pins in high-impedance state and tied to V

or V

, and all features that add delta

current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).

2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading

and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the
current consumption.
The test conditions for all I

measurements in active Operation mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to V

;

MCLR = V

; WDT enabled/disabled as specified.

3: For RC oscillator configurations, current through R

EXT

is not included. The current through the resistor can be estimated

by the formula Ir = V

/2R

EXT

(mA) with R

EXT

in k

PIC18FXX20

DS39609A-page 314

Advance Information

2003 Microchip Technology Inc.

Module Differential Currents (

WDT

BOR

LVD

OSCB

)

D022
(

WDT

)

Watchdog Timer

2.0

礎

-40

癈

= 2.0V

1.5

礎

癈

礎

癈

礎

-40

癈

= 3.0V

2.5

礎

癈

礎

癈

礎

-40

癈

= 5.0V

礎

癈

礎

癈

D022A

Brown-out Reset

礎

-40

癈 to +85癈

= 3.0V

(

BOR

)

礎

-40

癈 to +85癈

= 5.0V

D022B

Low Voltage Detect

礎

-40

癈 to +85癈

= 2.0V

(

LVD

)

礎

-40

癈 to +85癈

= 3.0V

礎

-40

癈 to +85癈

= 5.0V

D025

Timer1 Oscillator TBD

TBD

礎

-10

癈

(

OSCB

)

TBD

礎

癈

= 2.0V

32 kHz on Timer1

TBD

礎

癈

TBD

礎

-10

癈

TBD

礎

癈

= 3.0V

32 kHz on Timer1

TBD

礎

癈

TBD

礎

-10

癈

TBD

礎

癈

= 5.0V

32 kHz on Timer1

TBD

礎

癈

D026
(

)

A/D Converter

礎

癈

= 2.0V

礎

癈

= 3.0V

A/D on, not converting

礎

癈

= 5.0V

26.2

DC Characteristics: Power-down and Supply Current

PIC18FXX20 (Industrial, Extended)
PIC18LFXX20 (Industrial) (Continued)

PIC18LFXX20
(Industrial)

Standard Operating Conditions (unless otherwise stated)
Operating temperature

-40癈

+85癈 for industrial

PIC18FXX20
(Industrial, Extended)

Standard Operating Conditions (unless otherwise stated)
Operating temperature

-40癈

+85癈 for industrial

-40癈

+125癈 for extended

Param

No.

Device

Typ

Max

Units

Conditions

Legend: Shading of rows is to assist in readability of the table.
Note 1: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with

the part in SLEEP mode, with all I/O pins in high-impedance state and tied to V

or V

, and all features that add delta

current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).

2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading

and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the
current consumption.
The test conditions for all I

measurements in active Operation mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to V

;

MCLR = V

; WDT enabled/disabled as specified.

3: For RC oscillator configurations, current through R

EXT

is not included. The current through the resistor can be estimated

by the formula Ir = V

/2R

EXT

(mA) with R

EXT

in k

2003 Microchip Technology Inc.

Advance Information

DS39609A-page 315

PIC18FXX20

26.3

DC Characteristics: PIC18FXX20 (Industrial, Extended)

PIC18LFXX20 (Industrial)

DC CHARACTERISTICS

Standard Operating Conditions (unless otherwise stated)
Operating temperature -40癈

+85癈 for industrial

-40癈

+125癈 for extended

Param

No.

Symbol

Characteristic

Min

Max

Units

Conditions

Input Low Voltage
I/O ports:

D030

with TTL buffer

0.15 V

< 4.5V

D030A

0.8

4.5V

5.5V

D031

with Schmitt Trigger buffer
RC3 and RC4

0.2 V

0.3 V

V
V

D032

MCLR

0.2 V

D032A

OSC1 (in XT, HS and LP modes)
and T1OSI

0.3 V

D033

OSC1 (in RC and EC mode)

(1)

0.2 V

Input High Voltage
I/O ports:

D040

with TTL buffer

0.25 V

0.8V

< 4.5V

D040A

2.0

4.5V

5.5V

D041

with Schmitt Trigger buffer
RC3 and RC4

0.8 V

0.7 V

V
V

D042

MCLR, OSC1 (EC mode)

0.8 V

D042A

OSC1 (in XT, HS and LP modes)
and T1OSI

0.7 V

D043

OSC1 (RC mode)

(1)

0.9 V

Input Leakage Current

(2,3)

D060

I/O ports

�1

礎 V

Pin at hi-impedance

D061

MCLR

�5

礎 Vss V

D063

OSC1

�5

礎 Vss V

Weak Pull-up Current

D070

PURB

PORTB weak pull-up current

400

礎 V

= 5V, V

= V

Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the

PICmicro device be driven with an external clock while in RC mode.

2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified

levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.

3: Negative current is defined as current sourced by the pin.
4: Parameter is characterized but not tested.

PIC18FXX20

DS39609A-page 316

Advance Information

2003 Microchip Technology Inc.

Output Low Voltage

D080

I/O ports

0.6

= 8.5 mA, V

= 4.5V,

-40

癈 to +85癈

D080A

0.6

= 7.0 mA, V

= 4.5V,

-40

癈 to +125癈

D083

OSC2/CLKO
(RC mode)

0.6

= 1.6 mA, V

= 4.5V,

-40

癈 to +85癈

D083A

0.6

= 1.2 mA, V

= 4.5V,

-40

癈 to +125癈

Output High Voltage

(3)

D090

I/O ports

� 0.7

= -3.0 mA, V

= 4.5V,

-40

癈 to +85癈

D090A

� 0.7

= -2.5 mA, V

= 4.5V,

-40

癈 to +125癈

D092

OSC2/CLKO
(RC mode)

� 0.7

= -1.3 mA, V

= 4.5V,

-40

癈 to +85癈

D092A

� 0.7

= -1.0 mA, V

= 4.5V,

-40

癈 to +125癈

D150

Open Drain High Voltage

8.5

RA4 pin

Capacitive Loading Specs
on Output Pins

D100

(4)

OSC2

OSC2 pin

In XT, HS and LP modes
when external clock is used
to drive OSC1

D101

All I/O pins and OSC2
(in RC mode)

To meet the AC Timing
Specifications

D102

SCL, SDA

400

In I

C mode

26.3

DC Characteristics: PIC18FXX20 (Industrial, Extended)

PIC18LFXX20 (Industrial) (Continued)

DC CHARACTERISTICS

Standard Operating Conditions (unless otherwise stated)
Operating temperature -40癈

+85癈 for industrial

-40癈

+125癈 for extended

Param

No.

Symbol

Characteristic

Min

Max

Units

Conditions

Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the

PICmicro device be driven with an external clock while in RC mode.

2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified

levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.

3: Negative current is defined as current sourced by the pin.
4: Parameter is characterized but not tested.

2003 Microchip Technology Inc.

Advance Information

DS39609A-page 319

PIC18FXX20

TABLE 26-4:

MEMORY PROGRAMMING REQUIREMENTS

DC Characteristics

Standard Operating Conditions (unless otherwise stated)
Operating temperature -40癈

+85癈 for industrial

-40癈

+125癈 for extended

Param

No.

Sym

Characteristic

Min

Typ

Max

Units

Conditions

Internal Program Memory
Programming Specifications
(Note 1)

D110

Voltage on MCLR/V

9.00

13.25

(Note 2)

D112

Current into MCLR/V

礎

D113

DDP

Supply Current during
Programming

Data EEPROM Memory

D120

Cell Endurance

100K

E/W -40

癈 to +85癈

D120A E

Cell Endurance

10K

100K

E/W +85

癈 to +125癈

D121

DRW

for Read/Write

MIN

5.5

Using EECON to read/write
V

MIN

= Minimum operating

voltage

D122

DEW

Erase/Write Cycle Time

D123

RETD

Characteristic Retention

Year -40

癈 to +85癈 (Note 3)

D123A T

RETD

Characteristic Retention

100

Year 25

癈 (Note 3)

Program FLASH Memory

D130

Cell Endurance

10K

100K

E/W -40

癈 to +85癈

D130A E

Cell Endurance

1000

10K

E/W +85

癈 to +125癈

D131

for Read

MIN

5.5

MIN

= Minimum operating

voltage

D132

for Block Erase

4.5

5.5

Using ICSP port

D132A V

for Externally Timed Erase

or Write

4.5

5.5

Using ICSP port

D132B V

PEW

for Self-timed Write

MIN

5.5

MIN

= Minimum operating

voltage

D133

ICSP Block Erase Cycle Time

ms V

> 4.5V

D133A T

ICSP Erase or Write Cycle Time
(externally timed)

ms V

> 4.5V

D133A T

Self-timed Write Cycle Time

2.5

D134

RETD

Characteristic Retention

Year -40

癈 to +85癈 (Note 3)

D134A T

RETD

Characteristic Retention

100

Year 25

癈 (Note 3)

Data in "Typ" column is at 5.0V, 25癈 unless otherwise stated. These parameters are for design guidance
only and are not tested.

Note 1: These specifications are for programming the on-chip program memory through the use of Table Write

instructions.

2: The pin may be kept in this range at times other than programming, but it is not recommended.
3: Retention time is valid, provided no other specifications are violated.

PIC18FXX20

DS39609A-page 322

Advance Information

2003 Microchip Technology Inc.

26.4.3

TIMING DIAGRAMS AND SPECIFICATIONS

FIGURE 26-7:

EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL)

TABLE 26-6:

EXTERNAL CLOCK TIMING REQUIREMENTS

TABLE 26-7:

PLL CLOCK TIMING SPECIFICATIONS (V

= 4.2 TO 5.5V)

Param. No.

Symbol

Characteristic

Min

Max

Units

Conditions

OSC

External CLKI Frequency

(1)

MHz

EC, ECIO, PIC18FX620/X720

MHz

EC, ECIO, PIC18FX520

Oscillator Frequency

(1)

MHz

RC osc

0.1

MHz

XT osc

MHz

HS osc

MHz

HS + PLL osc, PIC18FX520

6.25

MHz

HS + PLL osc, PIC18FX620/X720

200

kHz

LP Osc mode

OSC

External CLKI Period

(1)

EC, ECIO, PIC18FX620/X720

160

EC, ECIO, PIC18FX520

Oscillator Period

(1)

250

RC osc

250

10,000

XT osc

100
100

250
250
160

ns
ns
ns

HS osc
HS + PLL osc, PIC18FX520
HS + PLL osc, PIC18FX620/X720

祍

LP osc

Instruction Cycle Time

(1)

100

= 4/F

OSC

TosL,
TosH

External Clock in (OSC1)
High or Low Time

XT osc

2.5

祍

LP osc

HS osc

TosR,
TosF

External Clock in (OSC1) Rise
or Fall Time

-- 20

osc

-- 50

osc

7.5

HS osc

Note 1: Instruction cycle period (T

) equals four times the input oscillator time-base period for all configurations except PLL. All

specified values are based on characterization data for that particular oscillator type under standard operating conditions
with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or
higher than expected current consumption. All devices are tested to operate at "min." values with an external clock applied
to the OSC1/CLKI pin. When an external clock input is used, the "max." cycle time limit is "DC" (no clock) for all devices.

Param. No.

Sym

Characteristic

Min

Typ

Max

Units

Conditions

OSC

Oscillator Frequency Range

MHz

HS mode

SYS

On-chip VCO System Frequency

MHz

HS mode

PLL Start-up Time (Lock Time)

CLK

CLKO Stability (Jitter)

-2

Data in "Typ" column is at 5V, 25

癈, unless otherwise stated. These parameters are for design guidance only and are not

tested.

OSC1

CLKO

2003 Microchip Technology Inc.

Advance Information

DS39609A-page 335

PIC18FXX20

TABLE 26-20: I

C BUS DATA REQUIREMENTS (SLAVE MODE)

Param.

No.

Symbol

Characteristic

Min

Max

Units

Conditions

100

HIGH

Clock high time

100 kHz mode

4.0

祍

PIC18FXX20 must operate
at a minimum of 1.5 MHz

400 kHz mode

0.6

祍

PIC18FXX20 must operate
at a minimum of 10 MHz

SSP Module

1.5 T

101

LOW

Clock low time

100 kHz mode

4.7

祍

PIC18FXX20 must operate
at a minimum of 1.5 MHz

400 kHz mode

1.3

祍

PIC18FXX20 must operate
at a minimum of 10 MHz

SSP Module

1.5 T

102

SDA and SCL rise
time

100 kHz mode

1000

400 kHz mode

20 + 0.1 C

300

is specified to be from

10 to 400 pF

103

SDA and SCL fall
time

100 kHz mode

300

400 kHz mode

20 + 0.1 C

300

is specified to be from

10 to 400 pF

STA

START condition
setup time

100 kHz mode

4.7

祍

Only relevant for Repeated
START condition

400 kHz mode

0.6

祍

STA

START condition
hold time

100 kHz mode

4.0

祍

After this period, the first
clock pulse is generated

400 kHz mode

0.6

祍

106

DAT

Data input hold
time

100 kHz mode

400 kHz mode

0.9

祍

107

DAT

Data input setup
time

100 kHz mode

250

(Note 2)

400 kHz mode

100

STO

STOP condition
setup time

100 kHz mode

4.7

祍

400 kHz mode

0.6

祍

109

Output valid from
clock

100 kHz mode

3500

(Note 1)

400 kHz mode

110

BUF

Bus free time

100 kHz mode

4.7

祍

Time the bus must be free
before a new transmission
can start

400 kHz mode

1.3

祍

D102

Bus capacitive loading

400

Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region

(min. 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.

2: A Fast mode I

C bus device can be used in a Standard mode I

C bus system, but the requirement

DAT

250 ns must then be met. This will automatically be the case if the device does not stretch the

LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must
output the next data bit to the SDA line.
T

max. + T

DAT

= 1000 + 250 = 1250 ns (according to the Standard mode I

C bus specification) before

the SCL line is released.

2003 Microchip Technology Inc.

Advance Information

DS39609A-page 337

PIC18FXX20

TABLE 26-22: MASTER SSP I

C BUS DATA REQUIREMENTS

Param.

No.

Symbol

Characteristic

Min

Max

Units

Conditions

100

HIGH

Clock high time 100 kHz mode

2(T

OSC

)(BRG + 1)

400 kHz mode

2(T

OSC

)(BRG + 1)

1 MHz mode

(1)

2(T

OSC

)(BRG + 1)

101

LOW

Clock low time

100 kHz mode

2(T

OSC

)(BRG + 1)

400 kHz mode

2(T

OSC

)(BRG + 1)

1 MHz mode

(1)

2(T

OSC

)(BRG + 1)

102

SDA and SCL
rise time

100 kHz mode

1000

is specified to be from

10 to 400 pF

400 kHz mode

20 + 0.1 C

300

1 MHz mode

(1)

300

103

SDA and SCL
fall time

100 kHz mode

300

is specified to be from

10 to 400 pF

400 kHz mode

20 + 0.1 C

300

1 MHz mode

(1)

100

STA

START condition
setup time

100 kHz mode

2(T

OSC

)(BRG + 1)

Only relevant for
Repeated START
condition

400 kHz mode

2(T

OSC

)(BRG + 1)

1 MHz mode

(1)

2(T

OSC

)(BRG + 1)

STA

START condition
hold time

100 kHz mode

2(T

OSC

)(BRG + 1)

After this period, the first
clock pulse is generated

400 kHz mode

2(T

OSC

)(BRG + 1)

1 MHz mode

(1)

2(T

OSC

)(BRG + 1)

106

DAT

Data input
hold time

100 kHz mode

400 kHz mode

0.9

1 MHz mode

(1)

TBD

107

DAT

Data input
setup time

100 kHz mode

250

(Note 2)

400 kHz mode

100

1 MHz mode

(1)

TBD

STO

STOP condition
setup time

100 kHz mode

2(T

OSC

)(BRG + 1)

400 kHz mode

2(T

OSC

)(BRG + 1)

1 MHz mode

(1)

2(T

OSC

)(BRG + 1)

109

Output valid from
clock

100 kHz mode

3500

400 kHz mode

1000

1 MHz mode

(1)

110

BUF

Bus free time

100 kHz mode

4.7

Time the bus must be free
before a new transmission
can start

400 kHz mode

1.3

1 MHz mode

(1)

TBD

D102

Bus capacitive loading

400

Note 1: Maximum pin capacitance = 10 pF for all I

C pins.

2: A Fast mode I

C bus device can be used in a Standard mode I

C bus system, but parameter #107

250 ns

must then be met. This will automatically be the case if the device does not stretch the LOW period of the
SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to
the SDA line, parameter #102 + parameter #107 = 1000 + 250 = 1250 ns (for 100 kHz mode) before the SCL
line is released.

2003 Microchip Technology Inc.

Advance Information

DS39609A-page 339

PIC18FXX20

TABLE 26-25: A/D CONVERTER CHARACTERISTICS: PIC18FXX20 (INDUSTRIAL, EXTENDED)

PIC18LFXX20 (INDUSTRIAL)

Param

No.

Symbol

Characteristic

Min

Typ

Max

Units

Conditions

A01

Resolution

--
--

TBD

bit
bit

REF

= V

3.0V

REF

= V

< 3.0V

A03

Integral linearity error

--
--

<�1

TBD

LSb
LSb

REF

= V

3.0V

REF

= V

< 3.0V

A04

Differential linearity error

--
--

<�1

TBD

LSb
LSb

REF

= V

3.0V

REF

= V

< 3.0V

A05

Full scale error

--
--

<�1

TBD

LSb
LSb

REF

= V

3.0V

REF

= V

< 3.0V

A06

OFF

Offset error

--
--

<�1

TBD

LSb
LSb

REF

= V

3.0V

REF

= V

< 3.0V

A10

Monotonicity

guaranteed

(3)

AIN

REF

A20

REF

Reference voltage
(V

REFH

- V

REFL

)

A20A

For 10-bit resolution

A21

REFH

Reference voltage High

AVss

+ 0.3V

A22

REFL

Reference voltage Low

AVss � 0.3V

A25

AIN

Analog input voltage

� 0.3V

REF

+ 0.3V

A30

AIN

Recommended impedance of
analog voltage source

10.0

A40

A/D conversion
current (V

)

PIC18FXX20

180

礎 Average current

consumption when
A/D is on (Note 1)

PIC18LFXX20

礎

A50

REF

input current (Note 2)

1000

礎

During V

AIN

acquisition.

Based on differential of
V

HOLD

to V

AIN

. To charge

HOLD

see Section 19.0.

During A/D conversion
cycle.

Note 1: When A/D is off, it will not consume any current other than minor leakage current. The power-down current

spec includes any such leakage from the A/D module.
V

REF

current is from RA2/AN2/V

REF

- and RA3/AN3/V

REF

+ pins or AV

and AV

pins, whichever is selected

as reference input.

2: Vss

AIN

REF

3: The A/D conversion result never decreases with an increase in the input voltage, and has no missing codes.

PIC18FXX20

DS39609A-page 340

Advance Information

2003 Microchip Technology Inc.

FIGURE 26-26:

A/D CONVERSION TIMING

TABLE 26-26: A/D CONVERSION REQUIREMENTS

131

130

132

BSF ADCON0, GO

A/D CLK

A/D DATA

ADRES

ADIF

SAMPLE

OLD_DATA

SAMPLING STOPPED

DONE

NEW_DATA

(Note 2)

Note 1: If the A/D clock source is selected as RC, a time of T

is added before the A/D clock starts. This allows the SLEEP instruction to be

executed.

2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.

. . .

Param.

No.

Symbol

Characteristic

Min

Max

Units

Conditions

130

A/D clock period

PIC18FXX20

1.6

(5)

祍

OSC

based, V

REF

3.0V

PIC18LFXX20

3.0

(5)

祍

OSC

based, V

REF

full range

PIC18FXX20

2.0

6.0

祍

A/D RC mode

PIC18LFXX20

3.0

9.0

祍

A/D RC mode

131

CNV

Conversion time
(not including acquisition time) (Note 1)

132

ACQ

Acquisition time (Note 3)

15
10

--
--

祍
祍

-40

癈 Temp 125癈

135

SWC

Switching time from convert

sample

(Note 4)

136

AMP

Amplifier settling time (Note 2)

祍

This may be used if the
"new" input voltage has not
changed by more than 1 LSb
(i.e., 5 mV @ 5.12V) from the
last sampled voltage (as
stated on C

HOLD

Note 1: ADRES register may be read on the following T

cycle.

2: See Section 19.0 for minimum conditions, when input voltage has changed more than 1 LSb.
3: The time for the holding capacitor to acquire the "New" input voltage, when the voltage changes full scale

after the conversion (AV

to AV

, or AV

to AV

). The source impedance (R

) on the input channels is

4: On the next Q4 cycle of the device clock.
5: The time of the A/D clock period is dependent on the device frequency and the T

clock divider.

2003 Microchip Technology Inc.

Advance Information

DS39609A-page 351

PIC18FXX20

INDEX

A/D ................................................................................... 213

A/D Converter Interrupt, Configuring ....................... 217
Acquisition Requirements ........................................ 218
Acquisition Time ....................................................... 218
ADCON0 Register .................................................... 213
ADCON1 Register .................................................... 213
ADCON2 Register .................................................... 213
ADRESH Register ............................................ 213, 216
ADRESL Register ............................................ 213, 216
Analog Port Pins ...................................................... 128
Analog Port Pins, Configuring .................................. 219
Associated Register Summary ................................. 221
Calculating Minimum Required

Acquisition Time (Example) ............................. 218

CCP2 Trigger ........................................................... 220
Configuring the Module ............................................ 217
Conversion Clock (T

) ........................................... 219

Conversion Requirements ....................................... 340
Conversion Status (GO/DONE Bit) .......................... 216
Conversion Tad Cycles ............................................ 220
Conversions ............................................................. 220
Converter Characteristics ........................................ 339
Equations ................................................................. 218
Minimum Charging Time .......................................... 218
Special Event Trigger (CCP) .................................... 152
Special Event Trigger (CCP2) .................................. 220
T

vs. Device Operating Frequencies (Table) ....... 219

Absolute Maximum Ratings ............................................. 307
AC (Timing) Characteristics ............................................. 320

Load Conditions for Device Timing

Specifications ................................................... 321

Parameter Symbology ............................................. 320
Temperature and Voltage Specifications ................. 321
Timing Conditions .................................................... 321

ACKSTAT Status Flag ..................................................... 187
ADCON0 Register ............................................................ 213

GO/DONE Bit ........................................................... 216

ADCON1 Register ............................................................ 213
ADCON2 Register ............................................................ 213
ADDLW ............................................................................ 265
Addressable Universal Synchronous Asynchronous

Receiver Transmitter (USART) ................................ 197

ADDWF ............................................................................ 265
ADDWFC ......................................................................... 266
ADRESH Register .................................................... 213, 216
ADRESL Register .................................................... 213, 216
Analog-to-Digital Converter. See A/D
ANDLW ............................................................................ 266
ANDWF ............................................................................ 267
Assembler

MPASM Assembler .................................................. 301

Baud Rate Generator ....................................................... 183
BC .................................................................................... 267
BCF .................................................................................. 268
BF Status Flag ................................................................. 187

Block Diagrams

16-bit Byte Select Mode ............................................. 75
16-bit Byte Write Mode .............................................. 73
16-bit Word Write Mode ............................................. 74
A/D ........................................................................... 216
Analog Input Model .................................................. 217
Baud Rate Generator .............................................. 183
Capture Mode Operation ......................................... 151
Comparator Analog Input Model .............................. 227
Comparator I/O Operating Modes (Diagram) .......... 224
Comparator Output .................................................. 226
Comparator Voltage Reference ............................... 230
Compare Mode Operation ....................................... 152
Low Voltage Detect (LVD) ....................................... 234
Low Voltage Detect (LVD) with External Input ......... 234
MSSP (I

C Master Mode) ........................................ 181

MSSP (I

C Mode) .................................................... 166

MSSP (SPI Mode) ................................................... 157
On-Chip Reset Circuit ................................................ 29
PIC18F6X20 Architecture ............................................ 9
PIC18F8X20 Architecture .......................................... 10
PLL ............................................................................ 23
PORT/LAT/TRIS Operation ..................................... 103
PORTA

RA3:RA0 and RA5 Pins ................................... 104
RA4/T0CKI Pin ................................................ 104
RA6 Pin (as I/O) .............................................. 104

PORTB

RB2:RB0 Pins .................................................. 107
RB3 Pin ........................................................... 107
RB7:RB4 Pins .................................................. 106

PORTC (Peripheral Output Override) ...................... 109
PORTD and PORTE

Parallel Slave Port ........................................... 128

PORTD in I/O Port Mode ......................................... 111
PORTD in System Bus Mode .................................. 112
PORTE in I/O Mode ................................................. 115
PORTE in System Bus Mode .................................. 115
PORTF

RF1/AN6/C2OUT and

RF2/AN5/C1OUT Pins ............................. 117

RF6/RF3 and RF0 Pins ................................... 118
RF7 Pin ............................................................ 118

PORTG (Peripheral Output Override) ...................... 120
PORTH

RH3:RH0 Pins in System Bus Mode ............... 123
RH3:RH0 Pins in I/O Mode .............................. 122
RH7:RH4 Pins in I/O Mode .............................. 122

PORTJ

RJ4:RJ0 Pins in System Bus Mode ................. 126
RJ7:RJ6 Pins in System Bus Mode ................. 126

PORTJ in I/O Mode ................................................. 125
PWM Operation (Simplified) .................................... 154
Reads from FLASH Program Memory ....................... 65
Single Comparator ................................................... 225
Table Read Operation ............................................... 61
Table Write Operation ................................................ 62
Table Writes to FLASH Program Memory ................. 67
Timer0 in 16-bit Mode .............................................. 132
Timer0 in 8-bit Mode ................................................ 132

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Timer1 ...................................................................... 136
Timer1 (16-bit R/W Mode) ........................................ 136
Timer2 ...................................................................... 142
Timer3 ...................................................................... 144
Timer3 in 16-bit R/W Mode ...................................... 144
Timer4 ...................................................................... 148
USART Receive ....................................................... 206
USART Transmit ...................................................... 204
Voltage Reference Output Buffer Example .............. 231
Watchdog Timer ....................................................... 251

BN .................................................................................... 268
BNC .................................................................................. 269
BNN .................................................................................. 269
BNOV ............................................................................... 270
BNZ .................................................................................. 270
BOR. See Brown-out Reset
BOV .................................................................................. 273
BRA .................................................................................. 271
BRG. See Baud Rate Generator
Brown-out Reset (BOR) ............................................. 30, 239
BSF .................................................................................. 271
BTFSC ............................................................................. 272
BTFSS .............................................................................. 272
BTG .................................................................................. 273
BZ ..................................................................................... 274

CALL ................................................................................ 274
Capture (CCP Module) ..................................................... 151

Associated Registers ............................................... 153
CCP Pin Configuration ............................................. 151
CCPR1H:CCPR1L Registers ................................... 151
Software Interrupt ..................................................... 151
Timer1/Timer3 Mode Selection ................................ 151

Capture/Compare/PWM (CCP) ........................................ 149

Capture Mode. See Capture
CCP Mode and Timer Resources ............................ 150
CCPRxH Register .................................................... 150
CCPRxL Register ..................................................... 150
Compare Mode. See Compare
Interconnect Configurations ..................................... 150
Module Configuration ............................................... 150
PWM Mode. See PWM

Capture/Compare/PWM Requirements ........................... 328
CLKO and I/O Timing Requirements ....................... 323, 324
Clocking Scheme/Instruction Cycle .................................... 44
CLRF ................................................................................ 275
CLRWDT .......................................................................... 275
Code Examples

16 x 16 Signed Multiply Routine ................................. 86
16 x 16 Unsigned Multiply Routine ............................. 86
8 x 8 Signed Multiply Routine ..................................... 85
8 x 8 Unsigned Multiply Routine ................................. 85
Changing Between Capture Prescalers ................... 151
Data EEPROM Read ................................................. 81
Data EEPROM Refresh Routine ................................ 82
Data EEPROM Write .................................................. 81
Erasing a FLASH Program Memory Row .................. 66
Fast Register Stack .................................................... 44
How to Clear RAM (Bank 1) Using

Indirect Addressing ............................................ 57

Implementing a Real-Time Clock Using a

Timer1 Interrupt Service .................................. 139

Initializing PORTA .................................................... 103
Initializing PORTB .................................................... 106
Initializing PORTC ................................................... 109
Initializing PORTD ................................................... 111
Initializing PORTE .................................................... 114
Initializing PORTF .................................................... 117
Initializing PORTG ................................................... 120
Initializing PORTH ................................................... 122
Initializing PORTJ .................................................... 125
Loading the SSPBUF (SSPSR) Register ................. 160
Reading a FLASH Program Memory Word ............... 65
Saving STATUS, WREG and BSR Registers

in RAM ............................................................. 102

Writing to FLASH Program Memory .....................69�70

Code Protection ............................................................... 239
COMF .............................................................................. 276
Comparator

Analog Input Connection Considerations ................ 227
Associated Registers ............................................... 228
Configuration ........................................................... 224
Effects of RESET ..................................................... 227
Interrupts .................................................................. 226
Operation ................................................................. 225
Operation During SLEEP ......................................... 227
Outputs .................................................................... 225
Reference ................................................................ 225

External Signal ................................................ 225
Internal Signal .................................................. 225

Response Time ........................................................ 225

Comparator Module ......................................................... 223
Comparator Specifications ............................................... 317
Comparator Voltage Reference ....................................... 229

Accuracy and Error .................................................. 230
Associated Registers ............................................... 231
Configuring .............................................................. 229
Connection Considerations ...................................... 230
Effects of a RESET .................................................. 230
Operation During SLEEP ......................................... 230

Compare (CCP Module) .................................................. 152

Associated Registers ............................................... 153
CCP Pin Configuration ............................................. 152
CCPR1 Register ...................................................... 152
Software Interrupt .................................................... 152
Special Event Trigger ...............................138, 145, 152
Timer1/Timer3 Mode Selection ................................ 152

Compare (CCP2 Module)

Special Event Trigger .............................................. 220

Configuration Bits ............................................................ 239
Context Saving During Interrupts ..................................... 102
Control Registers

EECON1 and EECON2 ............................................. 62
TABLAT (Table Latch) Register ................................. 64
TBLPTR (Table Pointer) Register .............................. 64

Conversion Considerations .............................................. 348
CPFSEQ .......................................................................... 276
CPFSGT .......................................................................... 277
CPFSLT ........................................................................... 277

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Data EEPROM Memory

Associated Registers ................................................. 83
EEADR Register ........................................................ 79
EEADRH Register ...................................................... 79
EECON1 Register ...................................................... 79
EECON2 Register ...................................................... 79
Operation During Code Protect .................................. 82
Protection Against Spurious Write ............................. 82
Reading ...................................................................... 81
Using .......................................................................... 82
Write Verify ................................................................ 82
Writing ........................................................................ 81

Data Memory ...................................................................... 47

General Purpose Registers ........................................ 47
Map for PIC18FX520 Devices ................................... 48
Map for PIC18FX620/X720 Devices .......................... 49
Special Function Registers ........................................ 47

DAW ................................................................................. 278
DC Characteristics

PIC18FXX20 (Industrial and Extended),

PIC18LFXX20 (Industrial) ................................ 315

Power-down and Supply Current ............................. 311
Supply Voltage ......................................................... 310

DCFSNZ ........................................................................... 279
DECF ............................................................................... 278
DECFSZ ........................................................................... 279
Development Support ...................................................... 301
Device Differences ........................................................... 347
Direct Addressing ............................................................... 58

Direct Addressing ....................................................... 56

Electrical Characteristics .................................................. 307
Errata ................................................................................... 5
Example SPI Mode Requirements (Master Mode,

CKE = 0) .................................................................. 330

Example SPI Mode Requirements (Master Mode,

CKE = 1) .................................................................. 331

Example SPI Mode Requirements (Slave Mode

CKE = 0) .................................................................. 332

Example SPI Slave Mode Requirements (CKE = 1) ........ 333
Extended Microcontroller Mode ......................................... 71
External Clock Timing Requirements ............................... 322
External Memory Interface ................................................. 71

16-bit Byte Select Mode ............................................. 75
16-bit Byte Write Mode .............................................. 73
16-bit Mode ................................................................ 73
16-bit Mode Timing .................................................... 76
16-bit Word Write Mode ............................................. 74
PIC18F8X20 External Bus - I/O Port Functions ......... 72
Program Memory Modes and External

Memory Interface ............................................... 71

Firmware Instructions ....................................................... 259
FLASH Program Memory ................................................... 61

Associated Registers ................................................. 70
Control Registers ....................................................... 62
Erase Sequence ........................................................ 66
Erasing ....................................................................... 66
Operation During Code Protect .................................. 70
Reading ...................................................................... 65

Table Pointer

Boundaries Based on Operation ....................... 64

Table Pointer Boundaries .......................................... 64
Table Reads and Table Writes .................................. 61
Write Sequence ......................................................... 68
Writing To .................................................................. 67

Protection Against Spurious Writes ................... 70
Unexpected Termination ................................... 70
Write Verify ........................................................ 70

General Call Address Support ......................................... 180
GOTO .............................................................................. 280

Hardware Multiplier ............................................................ 85

Introduction ................................................................ 85
Operation ................................................................... 85
Performance Comparison .......................................... 85

HS/PLL .............................................................................. 23

I/O Ports ........................................................................... 103
I

C Bus Data Requirements (Slave Mode) ...................... 335

C Bus START/STOP Bits Requirements

(Slave Mode) ........................................................... 334

C Mode

General Call Address Support ................................. 180
Master Mode

Operation ......................................................... 182

Master Mode Transmit Sequence ............................ 182
Read/Write Bit Information (R/W Bit) ................170, 171
Serial Clock (RC3/SCK/SCL) ................................... 171

ID Locations ..............................................................239, 257
INCF ................................................................................ 280
INCFSZ ............................................................................ 281
In-Circuit Debugger .......................................................... 257

Resources (Table) ................................................... 257

In-Circuit Serial Programming (ICSP) .......................239, 257
Indirect Addressing ............................................................ 58

INDF and FSR Registers ........................................... 57
Operation ................................................................... 57

Indirect Addressing Operation ........................................... 58
Indirect File Operand ......................................................... 47
INFSNZ ............................................................................ 281
Instruction Cycle ................................................................ 44
Instruction Flow/Pipelining ................................................. 45
Instruction Format ............................................................ 261
Instruction Set .................................................................. 259

ADDLW .................................................................... 265
ADDWF .................................................................... 265
ADDWFC ................................................................. 266
ANDLW .................................................................... 266
ANDWF .................................................................... 267
BC ............................................................................ 267
BCF ......................................................................... 268
BN ............................................................................ 268
BNC ......................................................................... 269
BNN ......................................................................... 269
BNOV ...................................................................... 270
BNZ ......................................................................... 270
BOV ......................................................................... 273
BRA ......................................................................... 271

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BSF .......................................................................... 271
BTFSC ..................................................................... 272
BTFSS ...................................................................... 272
BTG .......................................................................... 273
BZ ............................................................................. 274
CALL ........................................................................ 274
CLRF ........................................................................ 275
CLRWDT .................................................................. 275
COMF ....................................................................... 276
CPFSEQ .................................................................. 276
CPFSGT ................................................................... 277
CPFSLT ................................................................... 277
DAW ......................................................................... 278
DCFSNZ ................................................................... 279
DECF ....................................................................... 278
DECFSZ ................................................................... 279
GOTO ....................................................................... 280
INCF ......................................................................... 280
INCFSZ .................................................................... 281
INFSNZ .................................................................... 281
IORLW ..................................................................... 282
IORWF ..................................................................... 282
LFSR ........................................................................ 283
MOVF ....................................................................... 283
MOVFF ..................................................................... 284
MOVLB ..................................................................... 284
MOVLW .................................................................... 285
MOVWF ................................................................... 285
MULLW .................................................................... 286
MULWF .................................................................... 286
NEGF ....................................................................... 287
NOP ......................................................................... 287
POP .......................................................................... 288
PUSH ....................................................................... 288
RCALL ...................................................................... 289
RESET ..................................................................... 289
RETFIE .................................................................... 290
RETLW ..................................................................... 290
RETURN .................................................................. 291
RLCF ........................................................................ 291
RLNCF ..................................................................... 292
RRCF ....................................................................... 292
RRNCF ..................................................................... 293
SETF ........................................................................ 293
SLEEP ...................................................................... 294
SUBFWB .................................................................. 294
SUBLW .................................................................... 295
SUBWF .................................................................... 295
SUBWFB .................................................................. 296
SWAPF .................................................................... 296
TBLRD ..................................................................... 297
TBLWT ..................................................................... 298
TSTFSZ .................................................................... 299
XORLW .................................................................... 299
XORWF .................................................................... 300
Summary Table ........................................................ 262

INT Interrupt (RB0/INT). See Interrupt Sources
INTCON Registers ............................................................. 89
Inter-Integrated Circuit. See I

Interrupt Sources .............................................................. 239

A/D Conversion Complete ........................................ 217
Capture Complete (CCP) ......................................... 151
Compare Complete (CCP) ....................................... 152

INT0 ......................................................................... 102
Interrupt-on-Change (RB7:RB4) .............................. 106
PORTB, Interrupt-on-Change .................................. 102
RB0/INT Pin, External .............................................. 102
TMR0 ....................................................................... 102
TMR0 Overflow ........................................................ 133
TMR1 Overflow .................................................135, 138
TMR2 to PR2 Match ................................................ 142
TMR2 to PR2 Match (PWM) .............................141, 154
TMR3 Overflow .................................................143, 145
TMR4 to PR4 Match ................................................ 148
TMR4 to PR4 Match (PWM) .................................... 147

Interrupts ............................................................................ 87

Control Registers ....................................................... 89
Enable Registers ....................................................... 95
Flag Registers ............................................................ 92
Logic .......................................................................... 88
Priority Registers ....................................................... 98
RESET Control Registers ........................................ 101

IORLW ............................................................................. 282
IORWF ............................................................................. 282
IPR Registers ..................................................................... 98

Key Features

Easy Migration ............................................................. 7
Expanded Memory ....................................................... 7
External Memory Interface ........................................... 7
Other Special Features ................................................ 7

LFSR ................................................................................ 283
Low Voltage Detect .......................................................... 233

Characteristics ......................................................... 318
Converter Characteristics ........................................ 318
Effects of a RESET .................................................. 237
Operation ................................................................. 236

Current Consumption ....................................... 237
During SLEEP ................................................. 237
Reference Voltage Set Point ........................... 237

Typical Application ................................................... 233

Low Voltage ICSP Programming ..................................... 257
LVD. See Low Voltage Detect. ........................................ 233

Master SSP (MSSP) Module

Overview .................................................................. 157

Master SSP I

C Bus Data Requirements ........................ 337

Master SSP I

C Bus START/STOP Bits

Requirements .......................................................... 336

Master Synchronous Serial Port (MSSP). See MSSP.
Master Synchronous Serial Port. See MSSP
Memory Organization

Data Memory ............................................................. 47

Memory Programming Requirements .............................. 319
Microcontroller Mode ......................................................... 71
Microprocessor Mode ........................................................ 71
Microprocessor with Boot Block Mode ............................... 71
Migration from High-End to Enhanced Devices ............... 349
Migration from Mid-Range to Enhanced Devices ............ 348
MOVF .............................................................................. 283
MOVFF ............................................................................ 284
MOVLB ............................................................................ 284

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PIC18FXX20

MOVLW ............................................................................ 285
MOVWF ........................................................................... 285
MPLAB C17 and MPLAB C18 C Compilers ..................... 302
MPLAB ICD In-Circuit Debugger ...................................... 303
MPLAB ICE High Performance Universal In-Circuit

Emulator with MPLAB IDE ....................................... 303

MPLAB Integrated Development

Environment Software .............................................. 301

MPLINK Object Linker/MPLIB Object Librarian ............... 302
MSSP ............................................................................... 157

ACK Pulse ........................................................ 170, 171
Clock Stretching ....................................................... 176

10-bit Slave Receive Mode (SEN = 1) ............. 176
10-bit Slave Transmit Mode ............................. 176
7-bit Slave Receive Mode (SEN = 1) ............... 176
7-bit Slave Transmit Mode ............................... 176

Clock Synchronization and the CKP bit

(SEN = 1) ......................................................... 177

Control Registers (general) ...................................... 157
Enabling SPI I/O ...................................................... 161
I

C Mode .................................................................. 166

Acknowledge Sequence Timing ....................... 190
Baud Rate Generator ....................................... 183
Bus Collision During a Repeated START

Condition .................................................. 194

Bus Collision During a START Condition ......... 192
Bus Collision During a STOP Condition ........... 195
Clock Arbitration ............................................... 184
Effect of a RESET ............................................ 191
I

C Clock Rate w/BRG ..................................... 183

Master Mode .................................................... 181

Reception ................................................. 187
Repeated START Timing ......................... 186

Master Mode START Condition ....................... 185
Master Mode Transmission .............................. 187
Multi-Master Communication, Bus Collision

and Arbitration ......................................... 191

Multi-Master Mode ........................................... 191
Registers .......................................................... 166
SLEEP Operation ............................................. 191
STOP Condition Timing ................................... 190

C Mode. See I

Module Operation .................................................... 170
Operation ................................................................. 160
Slave Mode .............................................................. 170

Addressing ....................................................... 170
Reception ......................................................... 171
Transmission .................................................... 171

SPI

Master Mode .................................................... 162
SPI Clock ......................................................... 162

SPI Master Mode ..................................................... 162
SPI Mode ................................................................. 157
SPI Mode. See SPI
SPI Slave Mode ....................................................... 163

Select Synchronization .................................... 163

SSPBUF Register .................................................... 162
SSPSR Register ...................................................... 162
Typical Connection .................................................. 161

MSSP Module

SPI Master./Slave Connection ................................. 161

MULLW ............................................................................ 286
MULWF ............................................................................ 286

NEGF ............................................................................... 287
NOP ................................................................................. 287

OPCODE Field Descriptions ............................................ 260
OPTION_REG Register

PSA Bit .................................................................... 133
T0CS Bit .................................................................. 133
T0PS2:T0PS0 Bits ................................................... 133
T0SE Bit .................................................................. 133

Oscillator Configuration ..................................................... 21

EC .............................................................................. 21
ECIO .......................................................................... 21
HS .............................................................................. 21
HS + PLL ................................................................... 21
LP .............................................................................. 21
RC ............................................................................. 21
RCIO .......................................................................... 21
XT .............................................................................. 21

Oscillator Selection .......................................................... 239
Oscillator Switching Feature .............................................. 24

Oscillator Transitions ................................................. 26
System Clock Switch Bit ............................................ 25

Oscillator, Timer1 .............................................. 135, 137, 145
Oscillator, Timer3 ............................................................. 143
Oscillator, WDT ................................................................ 250

Packaging ........................................................................ 343

Details ...................................................................... 344
Marking .................................................................... 343

Parallel Slave Port (PSP) ..........................................111, 128

Associated Registers ............................................... 130
RE0/RD/AN5 Pin ..................................................... 128
RE1/WR/AN6 Pin ..................................................... 128
RE2/CS/AN7 Pin ...................................................... 128
Read Waveforms ..................................................... 130
Select (PSPMODE Bit) .....................................111, 128
Write Waveforms ..................................................... 129

Parallel Slave Port Requirements (PIC18F8X20) ............ 329
PICDEM 1 Low Cost PICmicro

Demonstration Board ............................................... 304

PICDEM 17 Demonstration Board ................................... 304
PICDEM 2 Low Cost PIC16CXX

Demonstration Board ............................................... 304

PICSTART Plus Entry Level Development

Programmer ............................................................. 303

PIE Registers ..................................................................... 95
Pin Functions

.......................................................................... 20

MCLR/V

................................................................. 11

OSC1/CLKI ................................................................ 11
OSC2/CLKO/RA6 ...................................................... 11
RA0/AN0 .................................................................... 12
RA1/AN1 .................................................................... 12
RA2/AN2/V

REF

- ......................................................... 12

RA3/AN3/V

REF

+ ........................................................ 12

RA4/T0CKI ................................................................ 12
RA5/AN4/LVDIN ........................................................ 12
RA6 ............................................................................ 12
RB0/INT0 ................................................................... 13

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RB1/INT1 ................................................................... 13
RB2/INT2 ................................................................... 13
RB3/INT3/CCP2 ......................................................... 13
RB4/KBI0 ................................................................... 13
RB5/KBI1/PGM .......................................................... 13
RB6/KBI2/PGC ........................................................... 13
RB7/KBI3/PGD ........................................................... 13
RC0/T1OSO/T13CKI .................................................. 14
RC1/T1OSI/CCP2 ...................................................... 14
RC2/CCP1 ................................................................. 14
RC3/SCK/SCL ............................................................ 14
RC4/SDI/SDA ............................................................. 14
RC5/SDO ................................................................... 14
RC6/TX1/CK1 ............................................................ 14
RC7/RX1/DT1 ............................................................ 14
RD0/PSP0/AD0 .......................................................... 15
RD1/PSP1/AD1 .......................................................... 15
RD2/PSP2/AD2 .......................................................... 15
RD3/PSP3/AD3 .......................................................... 15
RD4/PSP4/AD4 .......................................................... 15
RD5/PSP5/AD5 .......................................................... 15
RD6/PSP6/AD6 .......................................................... 15
RD7/PSP7/AD7 .......................................................... 15
RE0/RD/AD8 .............................................................. 16
RE1/WR/AD9 ............................................................. 16
RE2/CS/AD10 ............................................................ 16
RE3/AD11 .................................................................. 16
RE4/AD12 .................................................................. 16
RE5/AD13 .................................................................. 16
RE6/AD14 .................................................................. 16
RE7/CCP2/AD15 ........................................................ 16
RF0/AN5 .................................................................... 17
RF1/AN6/C2OUT ....................................................... 17
RF2/AN7/C1OUT ....................................................... 17
RF3/AN8 .................................................................... 17
RF4/AN9 .................................................................... 17
RF5/AN10/CV

REF

....................................................... 17

RF6/AN11 .................................................................. 17
RF7/SS ....................................................................... 17
RG0/CCP3 ................................................................. 18
RG1/TX2/CK2 ............................................................ 18
RG2/RX2/DT2 ............................................................ 18
RG3/CCP4 ................................................................. 18
RG4/CCP5 ................................................................. 18
RH0/A16 ..................................................................... 19
RH1/A17 ..................................................................... 19
RH2/A18 ..................................................................... 19
RH3/A19 ..................................................................... 19
RH4/AN12 .................................................................. 19
RH5/AN13 .................................................................. 19
RH6/AN14 .................................................................. 19
RH7/AN15 .................................................................. 19
RJ0/ALE ..................................................................... 20
RJ1/OE ....................................................................... 20
RJ2/WRL .................................................................... 20
RJ3/WRH ................................................................... 20
RJ4/BA0 ..................................................................... 20
RJ5/CE ....................................................................... 20
RJ6/LB ....................................................................... 20
RJ7/UB ....................................................................... 20
V

............................................................................. 20

PIR Registers ..................................................................... 92
PLL Clock Timing Specifications ...................................... 322
PLL Lock Time-out ............................................................. 30
Pointer, FSR ...................................................................... 57
POP ................................................................................. 288
POR. See Power-on Reset
PORTA

Associated Registers ............................................... 105
Functions ................................................................. 105
LATA Register ......................................................... 103
PORTA Register ...................................................... 103
TRISA Register ........................................................ 103

PORTB

Associated Registers ............................................... 108
Functions ................................................................. 108
LATB Register ......................................................... 106
PORTB Register ...................................................... 106
RB0/INT Pin, External .............................................. 102
TRISB Register ........................................................ 106

PORTC

Associated Registers ............................................... 110
Functions ................................................................. 110
LATC Register ......................................................... 109
PORTC Register ...................................................... 109
RC3/SCK/SCL Pin ................................................... 171
TRISC Register .................................................109, 197

PORTD ............................................................................ 128

Associated Registers ............................................... 113
Functions ................................................................. 113
LATD Register ......................................................... 111
Parallel Slave Port (PSP) Function .......................... 111
PORTD Register ...................................................... 111
TRISD Register ........................................................ 111

PORTE

Analog Port Pins ...................................................... 128
Associated Registers ............................................... 116
Functions ................................................................. 116
LATE Register ......................................................... 114
PORTE Register ...................................................... 114
PSP Mode Select (PSPMODE Bit) ...................111, 128
RE0/RD/AN5 Pin ..................................................... 128
RE1/WR/AN6 Pin ..................................................... 128
RE2/CS/AN7 Pin ...................................................... 128
TRISE Register ........................................................ 114

PORTF

Associated Registers ............................................... 119
Functions ................................................................. 119
LATF Register .......................................................... 117
PORTF Register ...................................................... 117
TRISF Register ........................................................ 117

PORTG

Associated Registers ............................................... 121
Functions ................................................................. 121
LATG Register ......................................................... 120
PORTG Register ...................................................... 120
TRISG Register ................................................120, 197

PORTH

Associated Registers ............................................... 124
Functions ................................................................. 124
LATH Register ......................................................... 122
PORTH Register ...................................................... 122
TRISH Register ........................................................ 122

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PORTJ

Associated Registers ............................................... 127
Functions ................................................................. 127
LATJ Register .......................................................... 125
PORTJ Register ....................................................... 125
TRISJ Register ......................................................... 125

Postscaler, WDT

Assignment (PSA Bit) .............................................. 133
Rate Select (T0PS2:T0PS0 Bits) ............................. 133
Switching Between Timer0 and WDT ...................... 133

Power-down Mode. See SLEEP
Power-on Reset (POR) .............................................. 30, 239

Oscillator Start-up Timer (OST) ......................... 30, 239
Power-up Timer (PWRT) ................................... 30, 239
Time-out Sequence .................................................... 30

Prescaler, Capture ........................................................... 151
Prescaler, Timer0 ............................................................. 133

Assignment (PSA Bit) .............................................. 133
Rate Select (T0PS2:T0PS0 Bits) ............................. 133
Switching Between Timer0 and WDT ...................... 133

Prescaler, Timer2 ............................................................. 154
PRO MATE II Universal Device Programmer .................. 303
Product Identification System ........................................... 363
Program Counter

PCL, PCLATH and PCLATU Registers ..................... 44

Program Memory ............................................................... 39

Access for PIC18F8X20 Program

Memory Modes .................................................. 40

Instructions ................................................................. 45
Interrupt Vector .......................................................... 39
Map and Stack for PIC18FXX20 ................................ 40
Maps for PIC18F8X20 Program

Memory Modes .................................................. 41

PIC18F8X20 Modes ................................................... 39
RESET Vector ............................................................ 39

Program Memory Write Timing Requirements ................. 325
Program Verification and Code Protection ....................... 253

Associated Registers ............................................... 253
Configuration Register Protection ............................ 257
Data EEPROM Code Protection .............................. 257
Memory Code Protection ......................................... 255

Programming, Device Instructions ................................... 259
PSP.See Parallel Slave Port.
Pulse Width Modulation. See PWM (CCP Module).
PUSH ............................................................................... 288
PWM (CCP Module) ......................................................... 154

Associated Registers ............................................... 155
CCPR1H:CCPR1L Registers ................................... 154
Duty Cycle ................................................................ 154
Example Frequencies/Resolutions .......................... 155
Period ....................................................................... 154
Setup for PWM Operation ........................................ 155
TMR2 to PR2 Match ........................................ 141, 154
TMR4 to PR4 Match ................................................ 147

Q Clock ............................................................................ 154

RAM. See Data Memory
RC Oscillator ...................................................................... 22
RCALL ............................................................................. 289
RCON Registers .............................................................. 101
RCSTA Register

SPEN Bit .................................................................. 197

ADCON0 (A/D Control 0) ......................................... 213
ADCON1 (A/D Control 1) ......................................... 214
ADCON2 (A/D Control 2) ......................................... 215
CCPxCON (Capture/Compare/

PWM Control) .................................................. 149

CMCON (Comparator Control) ................................ 223
CONFIG1H (Configuration 1 High) .......................... 241
CONFIG2H (Configuration 2 High) .......................... 242
CONFIG2L (Configuration 2 Low) ........................... 241
CONFIG3H (Configuration 3 High) .......................... 243
CONFIG3L (Configuration 3 Low) ........................... 242
CONFIG3L (Configuration Byte) ................................ 41
CONFIG4L (Configuration 4 Low) ........................... 243
CONFIG5H (Configuration 5 High) .......................... 245
CONFIG5L (Configuration 5 Low) ........................... 244
CONFIG6H (Configuration 6 High) .......................... 247
CONFIG6L (Configuration 6 Low) ........................... 246
CONFIG7H (Configuration 7 High) .......................... 249
CONFIG7L (Configuration 7 Low) ........................... 248
CVRCON (Comparator Voltage

Reference Control) .......................................... 229

Device ID 1 .............................................................. 249
Device ID 2 .............................................................. 249
EECON1 (Data EEPROM Control 1) ....................63, 80
INTCON (Interrupt Control) ........................................ 89
INTCON2 (Interrupt Control 2) ................................... 90
INTCON3 (Interrupt Control 3) ................................... 91
IPR1 (Peripheral Interrupt Priority 1) ......................... 98
IPR2 (Peripheral Interrupt Priority 2) ......................... 99
IPR3 (Peripheral Interrupt Priority 3) ....................... 100
LVDCON (LVD Control) ........................................... 235
MEMCON (Memory Control) ..................................... 71
OSCCON ................................................................... 25
PIE1 (Peripheral Interrupt Enable 1) .......................... 95
PIE2 (Peripheral Interrupt Enable 2) .......................... 96
PIE3 (Peripheral Interrupt Enable 3) .......................... 97
PIR1 (Peripheral Interrupt Request 1) ....................... 92
PIR2 (Peripheral Interrupt Request 2) ....................... 93
PIR3 (Peripheral Interrupt Request 3) ....................... 94
PSPCON (Parallel Slave Port Control) .................... 129
RCON ........................................................................ 31
RCON (Reset Control) ........................................60, 101
RCSTAx (Receive Status and Control) .................... 199
SSPCON1 (MSSP Control 1) - I

C Mode ................ 168

SSPCON1 (MSSP Control 1) - SPI Mode ............... 159
SSPCON2 (MSSP Control 2) - I

C Mode ................ 169

SSPSTAT (MSSP Status) - I

C Mode ..................... 167

SSPSTAT (MSSP Status) - SPI Mode ..................... 158
STATUS .................................................................... 59
STKPTR (Stack Pointer) ............................................ 43
Summary ..............................................................52�55

PIC18FXX20

DS39609A-page 358

Advance Information

2003 Microchip Technology Inc.

T0CON (Timer0 Control) .......................................... 131
T1CON (Timer 1 Control) ......................................... 135
T2CON (Timer 2 Control) ......................................... 141
T3CON (Timer3 Control) .......................................... 143
T4CON (Timer4 Control) .......................................... 147
TXSTAx (Transmit Status and Control) .................... 198
WDTCON (Watchdog Timer Control) ....................... 250

RESET ............................................................... 29, 239, 289

MCLR Reset ............................................................... 29
MCLR Reset during SLEEP ....................................... 29
Power-on Reset (POR) .............................................. 29
Programmable Brown-out Reset (PBOR) .................. 29
RESET Instruction ...................................................... 29
Stack Full Reset ......................................................... 29
Stack Underflow Reset ............................................... 29
Watchdog Timer (WDT) Reset ................................... 29

RESET, Watchdog Timer, Oscillator Start-up Timer,

Power-up Timer and Brown-out Reset
Requirements ........................................................... 326

RETFIE ............................................................................ 290
RETLW ............................................................................. 290
RETURN .......................................................................... 291
Return Address Stack

and Associated Registers .......................................... 43

Revision History ............................................................... 347
RLCF ................................................................................ 291
RLNCF ............................................................................. 292
RRCF ............................................................................... 292
RRNCF ............................................................................. 293

SCI. See USART
SCK .................................................................................. 157
SDI ................................................................................... 157
SDO ................................................................................. 157
Serial Clock, SCK ............................................................. 157
Serial Communication Interface. See USART
Serial Data In, SDI ........................................................... 157
Serial Data Out, SDO ....................................................... 157
Serial Peripheral Interface. See SPI
SETF ................................................................................ 293
Slave Select, SS .............................................................. 157
SLEEP .............................................................. 239, 252, 294
Software Simulator (MPLAB SIM) .................................... 302
Special Event Trigger. See Compare
Special Features of the CPU ............................................ 239

Configuration Registers .................................... 241�249

Special Function Registers ................................................ 47

Map ............................................................................ 50

SPI

Serial Clock .............................................................. 157
Serial Data In ........................................................... 157
Serial Data Out ......................................................... 157
Slave Select ............................................................. 157
SPI Mode ................................................................. 157

SPI Master/Slave Connection .......................................... 161
SPI Module

Associated Registers ............................................... 165
Bus Mode Compatibility ........................................... 165
Effects of a RESET .................................................. 165
Master/Slave Connection ......................................... 161
Slave Mode .............................................................. 163
SLEEP Operation ..................................................... 165

SS .................................................................................... 157
SSP

TMR2 Output for Clock Shift .............................141, 142
TMR4 Output for Clock Shift .................................... 148

SSPOV Status Flag ......................................................... 187
SSPSTAT Register

R/W Bit ..............................................................170, 171

STATUS Bits

Significance and Initialization Condition for

RCON Register .................................................. 31

SUBFWB ......................................................................... 294
SUBLW ............................................................................ 295
SUBWF ............................................................................ 295
SUBWFB ......................................................................... 296
SWAPF ............................................................................ 296

Table Pointer Operations (table) ........................................ 64
TBLRD ............................................................................. 297
TBLWT ............................................................................. 298
Time-out in Various Situations ........................................... 31
Timer0 .............................................................................. 131

16-bit Mode Timer Reads and Writes ...................... 133
Associated Registers ............................................... 133
Clock Source Edge Select (T0SE Bit) ..................... 133
Clock Source Select (T0CS Bit) ............................... 133
Operation ................................................................. 133
Overflow Interrupt .................................................... 133
Prescaler. See Prescaler, Timer0

Timer0 and Timer1 External Clock

Requirements .......................................................... 327

Timer1 .............................................................................. 135

16-bit Read/Write Mode ........................................... 138
Associated Registers ............................................... 139
Operation ................................................................. 136
Oscillator ...........................................................135, 137
Overflow Interrupt .............................................135, 138
Special Event Trigger (CCP) ............................138, 152
TMR1H Register ...................................................... 135
TMR1L Register ....................................................... 135
Use as a Real-Time Clock ....................................... 138

Timer2 .............................................................................. 141

Associated Registers ............................................... 142
Operation ................................................................. 141
Postscaler. See Postscaler, Timer2
PR2 Register ....................................................141, 154
Prescaler. See Prescaler, Timer2
SSP Clock Shift ................................................141, 142
TMR2 Register ......................................................... 141
TMR2 to PR2 Match Interrupt ...................141, 142, 154

Timer3 .............................................................................. 143

Associated Registers ............................................... 145
Operation ................................................................. 144
Oscillator ...........................................................143, 145
Overflow Interrupt .............................................143, 145
Special Event Trigger (CCP) ................................... 145
TMR3H Register ...................................................... 143
TMR3L Register ....................................................... 143

2003 Microchip Technology Inc.

Advance Information

DS39609A-page 359

PIC18FXX20

Timer4 .............................................................................. 147

Associated Registers ............................................... 148
Operation ................................................................. 147
Postscaler. See Postscaler, Timer4
PR4 Register ............................................................ 147
Prescaler. See Prescaler, Timer4
SSP Clock Shift ........................................................ 148
TMR4 Register ......................................................... 147
TMR4 to PR4 Match Interrupt .......................... 147, 148

Timing Diagrams

A/D Conversion ........................................................ 340
Acknowledge Sequence .......................................... 190
Baud Rate Generator with Clock

Arbitration ......................................................... 184

BRG Reset Due to SDA Arbitration During

START Condition ............................................. 193

Brown-out Reset (BOR) ........................................... 326
Bus Collision During a Repeated START

Condition (Case 1) ........................................... 194

Bus Collision During a Repeated START

Condition (Case 2) ........................................... 194

Bus Collision During a START Condition

(SCL = 0) ......................................................... 193

Bus Collision During a STOP Condition

(Case 1) ........................................................... 195

Bus Collision During a STOP Condition

(Case 2) ........................................................... 195

Bus Collision During START Condition

(SDA only) ........................................................ 192

Bus Collision for Transmit and Acknowledge ........... 191
Capture/Compare/PWM (All CCP Modules) ............ 328
CLKO and I/O .......................................................... 323
Clock Synchronization ............................................. 177
Clock/Instruction Cycle .............................................. 44
Example SPI Master Mode (CKE = 0) ..................... 330
Example SPI Master Mode (CKE = 1) ..................... 331
Example SPI Slave Mode (CKE = 0) ....................... 332
Example SPI Slave Mode (CKE = 1) ....................... 333
External Clock (All Modes except PLL) .................... 322
External Memory Bus for SLEEP

(Microprocessor Mode) ...................................... 77

External Memory Bus for TBLRD (Extended

Microcontroller Mode) ........................................ 76

External Memory Bus for TBLRD

(Microprocessor Mode) ...................................... 76

C Bus Data ............................................................ 334

C Bus START/STOP Bits ...................................... 334

C Master Mode (7 or 10-bit Transmission) ............ 188

C Master Mode (7-bit Reception) .......................... 189

C Master Mode First START Bit Timing ................ 185

C Slave Mode (10-bit Reception,

SEN = 0) .......................................................... 174

C Slave Mode (10-bit Reception,

SEN = 1) .......................................................... 179

C Slave Mode (10-bit Transmission) ..................... 175

C Slave Mode (7-bit Reception, SEN = 0) ............. 172

C Slave Mode (7-bit Reception, SEN = 1) ............. 178

C Slave Mode (7-bit Transmission) ....................... 173

Low Voltage Detect .................................................. 236
Master SSP I

C Bus Data ........................................ 336

Master SSP I

C Bus START/STOP Bits .................. 336

Parallel Slave Port (PIC18F8X20) ........................... 329
Program Memory Read ............................................ 324

Program Memory Write ............................................ 325
PWM Output ............................................................ 154
Repeat START Condition ........................................ 186
RESET, Watchdog Timer (WDT), Oscillator

Start-up Timer (OST) and Power-up
Timer (PWRT) ................................................. 326

Slave Mode General Call Address Sequence

(7 or 10-bit Address Mode) .............................. 180

Slave Synchronization ............................................. 163
Slow Rise Time (MCLR Tied to V

via

1 kOhm Resistor) ............................................... 38

SPI Mode (Master Mode) ......................................... 162
SPI Mode (Slave Mode with CKE = 0) ..................... 164
SPI Mode (Slave Mode with CKE = 1) ..................... 164
STOP Condition Receive or Transmit Mode ............ 190
Synchronous Reception (Master Mode,

SREN) ............................................................. 210

Synchronous Transmission ..................................... 209
Synchronous Transmission (Through TXEN) .......... 209
Time-out Sequence on POR w/PLL Enabled

(MCLR Tied to V

via 1 kOhm Resistor) ......... 38

Time-out Sequence on Power-up

(MCLR Not Tied to V

)

Case 1 ............................................................... 37
Case 2 ............................................................... 37

Time-out Sequence on Power-up (MCLR Tied

to V

via 1 kOhm Resistor) ............................. 37

Timer0 and Timer1 External Clock .......................... 327
Timing for Transition Between Timer1 and

OSC1 (HS with PLL) .......................................... 27

Transition Between Timer1 and OSC1

(HS, XT, LP) ...................................................... 26

Transition Between Timer1 and OSC1

(RC, EC) ............................................................ 27

Transition from OSC1 to Timer1 Oscillator ................ 26
USART Asynchronous Reception ............................ 207
USART Asynchronous Transmission ...................... 205
USART Asynchronous Transmission

(Back to Back) ................................................. 205

USART Synchronous Receive

(Master/Slave) ................................................. 338

USART Synchronous Transmission

(Master/Slave) ................................................. 338

Wake-up from SLEEP via Interrupt .......................... 253

TRISE Register

PSPMODE Bit ...................................................111, 128

TSTFSZ ........................................................................... 299
Two-Word Instructions

Example Cases .......................................................... 46

TXSTA Register

BRGH Bit ................................................................. 200

PIC18FXX20

DS39609A-page 360

Advance Information

2003 Microchip Technology Inc.

Universal Synchronous Asynchronous Receiver

Transmitter. See USART

USART

Asynchronous Mode ................................................ 204

Associated Registers, Receive ........................ 207
Associated Registers, Transmit ....................... 205
Receiver ........................................................... 206
Setting up 9-bit Mode with Address Detect ...... 206
Transmitter ....................................................... 204

Baud Rate Generator (BRG) .................................... 200

Associated Registers ....................................... 200
Baud Rate Error, Calculating ........................... 200
Baud Rate Formula .......................................... 200
Baud Rates for Asynchronous Mode

(BRGH = 0) .............................................. 202

Baud Rates for Asynchronous Mode

(BRGH = 1) .............................................. 203

Baud Rates for Synchronous Mode ................. 201
High Baud Rate Select (BRGH Bit) .................. 200
Sampling .......................................................... 200

Serial Port Enable (SPEN Bit) .................................. 197
Synchronous Master Mode ...................................... 208

Associated Registers, Reception ..................... 210
Associated Registers, Transmit ....................... 208
Reception ......................................................... 210
Transmission .................................................... 208

Synchronous Slave Mode ........................................ 211

Associated Registers, Receive ........................ 212
Associated Registers, Transmit ....................... 211
Reception ......................................................... 212
Transmission .................................................... 211

USART Synchronous Receive Requirements .................. 338
USART Synchronous Transmission Requirements ......... 338

Voltage Reference Specifications .................................... 317

Wake-up from SLEEP ...............................................239, 252

Using Interrupts ....................................................... 252

Watchdog Timer (WDT) ............................................239, 250

Associated Registers ............................................... 251
Control Register ....................................................... 250
Postscaler ................................................................ 251
Programming Considerations .................................. 250
RC Oscillator ............................................................ 250
Time-out Period ....................................................... 250

WCOL .............................................................................. 185
WCOL Status Flag .................................... 185, 186, 187, 190
WDT Postscaler ............................................................... 250
WWW, On-Line Support ...................................................... 5

XORLW ............................................................................ 299
XORWF ........................................................................... 300

2003 Microchip Technology Inc.

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DS39609A-page 361

PIC18FXX20

ON-LINE SUPPORT

Microchip provides on-line support on the Microchip
World Wide Web site.
The web site is used by Microchip as a means to make
files and information easily available to customers. To
view the site, the user must have access to the Internet
and a web browser, such as Netscape

�

or Microsoft

�

Internet Explorer. Files are also available for FTP
download from our FTP site.

Connecting to the Microchip Internet Web Site

The Microchip web site is available at the following
URL:

www.microchip.com

The file transfer site is available by using an FTP ser-
vice to connect to:

ftp://ftp.microchip.com

The web site and file transfer site provide a variety of
services. Users may download files for the latest
Development Tools, Data Sheets, Application Notes,
User's Guides, Articles and Sample Programs. A vari-
ety of Microchip specific business information is also
available, including listings of Microchip sales offices,
distributors and factory representatives. Other data
available for consideration is:
� Latest Microchip Press Releases
� Technical Support Section with Frequently Asked

Questions

� Design Tips
� Device Errata
� Job Postings
� Microchip Consultant Program Member Listing
� Links to other useful web sites related to

Microchip Products

� Conferences for products, Development Systems,

technical information and more

� Listing of seminars and events

SYSTEMS INFORMATION AND
UPGRADE HOT LINE

The Systems Information and Upgrade Line provides
system users a listing of the latest versions of all of
Microchip's development systems software products.
Plus, this line provides information on how customers
can receive the most current upgrade kits.The Hot Line
Numbers are:
1-800-755-2345 for U.S. and most of Canada, and
1-480-792-7302 for the rest of the world.

092002

DS39609A-page 364

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AMERICAS

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12/05/02

ORLDWIDE

ALES

AND

ERVICE

协谢械泻褌褉芯薪薪褘泄泻芯屑锌芯薪械薪褌: PIC18F6620

Document Outline

协谢械泻褌褉芯薪薪褘泄 泻芯屑锌芯薪械薪褌: PIC18F6620

Document Outline

协谢械泻褌褉芯薪薪褘泄泻芯屑锌芯薪械薪褌: PIC18F6620